📄 la.asm
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;CPU改为2313的源程序，硬件改动见程序中管脚定义
; Logic-Analyzer and PulseGenerator
; Version 0.16 CPU改为2313
; Version 0.15 Neu: PulseGenerator-Modes. Erwartet 7 Bytes!
; Version 0.09 Verkuerzte Routine fuer cntclk und ram_wr
; Version 0.07 Neue Modes fuer Test-Routinen
; Version 0.06 Anpassung an AT90S1200
; Version 0.05 funktionsfaehig fuer AT90S2313
;
; 串口控制字符/LogicAnalyzer: / PulseGen:
; 1. TriggerByte (触发字节) / TiL
; 2. Masken-Byte (为1的位don't care) / TiH
; 3. Timer-Intervall / TpL
; 4. Timer-Prescaler / TpH
; 5. Pre-Trigger in 256-Byte Schritten; / TnL
; 6. unbenutzt / TnH
; 7. Modus-Byte (int-/ext-Clock, int-/ext-Trigger) / Mode
;
; 假设 Triggerword: 0 1 1 0 X X X 1
; TriggerByte: 0 1 1 0 1 1 1 1
; Masken-Byte: 0 0 0 0 1 1 1 0
;
; Sampling-Byte: 0 1 1 0 0 1 1 1
; mit Masken-OR: 0 1 1 0 1 1 1 1 = TriggerByte --> TRIGGER!
;
.nolist
.include ".\2313def.inc"
.list
.def TpCntH = R27 ;PulseGen: Tp-Counter-High
.def TpCntL = R26 ;PulseGen: Tp-Counter-Low
.def TiCntH = R25 ;PulseGen: Ti-Counter-High
.def TiCntL = R24 ;PulseGen: Ti-Counter-Low
.def temp = R23 ;temporary storage register
.def bitcnt = R22 ;bit counter
.def TXbyte = R21 ;Data to be transmitted
.def RXbyte = R20 ;Received data
.def bufcntH = R19 ;Ringspeicher-Zaehler High
.def TnCntH = R19 ;PulseGen: Burst-Count-High
.def bufcntL = R18 ;Ringspeicher-Zaehler Low
.def TnCntL = R18 ;PulseGen: Burst-Count-Low
.def mode = R17 ;Modus
.def wreg = R16 ;Working-Register
.def trig = R15 ;Trigger-Register
.def TiL = R15 ;低电平持续时间(PulseGen)
.def mask = R14 ;Masken-Register
.def TiH = R14 ;高电平持续时间(PulseGen)
.def timereg = R13 ;fuer Timervergleich
.def TnH = R13 ;(PulseGen)
.def prescal = R12 ;Timer PreScaler
.def TpH = R12 ;(PulseGen)
.def delta = R11 ;Timer-Intervall
.def TpL = R11 ;(PulseGen)
.def pretrig = R10 ;Pre-Trigger
.def TnL = R10 ;(PulseGen)
.def aux1 = R9 ;Hilfsregister
.def aux0 = R8 ;Hilfsregister
.def store1 = R7 ;PORTD, cntclk=H und ram_wr=L
.def store2 = R6 ;PORTD, cntclk=L und ram_wr=H (Ruhezustand)
;---------------------------------------------------------------------------
;Hardware Definition
;
;Baudrate 38400:
.equ baud = 25 ;16MHz Quart (90S3212) fosc/(16*BAUD) - 1
;
;Port-Pinbelegung:
.equ ram_wr = PD5 ;RAM /WR Write-Enable (Low-aktiv)
.equ ram_oe = PD4 ;RAM /OE Output-Enable (Low-aktiv)
.equ sample = PD6 ;Clock (positiv) und Output-Enable (Low) des 74HC574
.equ PGout = PD2 ;PulseGenerator Output
.equ cntclk = PD3 ;Clock (positiv) des Ripple-Counters 74HC4040
.equ RxD = PD0 ;RxD
.equ TxD = PD1 ;TxD
.equ extpin = PB0 ;Externer Trigger-/Clock-Eingang an Port-B
;
;---------------------------------------------------------------------------
.org 0x0000
rjmp start ;Sprung nach Reset
reti ;INT0
reti ;INT1
reti ;TMR1 CAPT1
reti ;TMR1 COMP1
reti ;TMR1 OVF
reti ;TMR0 OVF
rjmp RAMfull ;UART RXI 程序中断捕获
reti ;UART UDRE
reti ;UART TXI
reti ;ANA COMP
start:
;-------------------------------------------------------------------
;Stackpointer initialization
;-------------------------------------------------------------------
ldi wreg,low(RAMEND)
out SPL,wreg
;-------------------------------------------------------------------
;Ports initialization
;-------------------------------------------------------------------
ldi wreg,0b01111011 ;PORT-D Richtungs-Register
out DDRD,wreg ;
ldi wreg,0b11110010 ;PORT-D Ausgabezustand
;cntclk = low
;TxD = high
;RxD = input, External Pull-Up
;PGout = low
;sample = high
;ram_oe = inactive (high)
;ram_wr = inactive (high)
out PORTD,wreg ;PORT-D
mov store2,wreg ;store2 无SRAM操作时IO状态
ldi wreg,0b11011010 ;cntclk=high, ram_wr=low
mov store1,wreg ;store1 写SRAM时IO状态
ldi wreg,0b00000000 ;PORT-B Register
out DDRB,wreg ;全部为输入
out PORTB,wreg ;无Pull-Up
;-------------------------------------------------------------------
;UART initialization
;-------------------------------------------------------------------
ldi wreg,0b00011000 ;8bit mode, enable RXEN & TXEN
out UCR,wreg
ldi wreg,baud
out UBRR,wreg
;-------------------------------------------------------------------
;ADIW auxial register aux0 und aux1
;-------------------------------------------------------------------
ldi wreg,0x00 ;Hilfsregister-0 mit 0 laden
mov aux0,wreg ;"
ldi wreg,0x01 ;Hilfsregister-1 mit 1 laden
mov aux1,wreg ;"
;-------------------------------------------------------------------
;等待串口初始化字符串
;-------------------------------------------------------------------
rcall getchar
in trig,UDR ; = TiL
rcall getchar
in mask,UDR ; = TiH
rcall getchar
in delta,UDR ; = TpL
rcall getchar
in prescal,UDR ; = TpH
rcall getchar
in pretrig,UDR ; = TnL
rcall getchar
in TnH,UDR ; bei LogicAnalyzer ignoriert
rcall getchar
in mode,UDR
;-------------------------------------------------------------------
;EXTINT & UART 中断设置
;-------------------------------------------------------------------
ldi wreg,0x00 ;
out GIMSK,wreg ;
ldi wreg,0x00 ;
out MCUCR,wreg ;
sbi UCR,RXCIE ;允许串口接收中断
sei ;允许全局中断
;-------------------------------------------------------------------
;PulseGenerator-Modes filtern
;-------------------------------------------------------------------
PGMode10:
cpi mode,10 ;Range-1, Continous
brne PGMode11
rjmp PG_Start0
PGMode11:
cpi mode,11 ;Range-1, Burst
brne PGMode12
rjmp PG_Start1
PGMode12:
cpi mode,12 ;Range-2, Continous
brne PGMode13
rjmp PG_Start2
PGMode13:
cpi mode,13 ;Range-2, Burst
brne ClearRAM
rjmp PG_Start3
;-------------------------------------------------------------------
;RAM-Speicher loeschen
;-------------------------------------------------------------------
ClearRAM:
ldi bufcntL,LOW (0x0000-2048) ;Alle 2048 Speicherplaetze
ldi bufcntH,HIGH(0x0000-2048) ;loeschen
ldi wreg,0xFF ;PORTB auf ausgabe
out DDRB,wreg ;"
ldi wreg,0x00 ;Bitmuster anlegen
out PORTB,wreg ;"
RAMclr:
out PORTD,store1 ;RAM schreiben und
out PORTD,store2 ;Counter increment.
nop ;
add bufcntL,aux1 ;incr. BufferCounter
adc bufcntH,aux0 ;"
brcc RAMclr
ldi wreg,0x00 ;PORTB auf eingabe
out DDRB,wreg ;"
ldi wreg,0b11111111 ;PORT-B
out PORTB,wreg ;Pull-Ups aktivieren
cbi PORTD,sample ;register auf BUS legen
;-------------------------------------------------------------------
;预触发位置初始化
;z.B.: 0% PreTrigger-Wert=8, $00-$08=$F8 (high-Byte)
;Sample-Nr.0 ist Triggersample, es muessen noch 2047 Samples folgen.
;Samplezahl=$0000-2047=$F801
;z.B.: 25% PreTrigger-Wert=6, $00-$06=$FA (high-Byte)
;Sample-Nr. 512 ist Triggersample, es muessen noch 1535 Samples folgen.
;Samplezahl=$0000-1535=$FA01
;-------------------------------------------------------------------
ldi wreg,0x00
sub wreg,pretrig
ldi bufcntL,0x01
mov bufcntH,wreg
;-------------------------------------------------------------------
;Mode auswerten und passende Routine aufrufen (Logic-Analyzer)
;-------------------------------------------------------------------
Mode0:
cpi mode,0 ;internal Clock, internal Trigger
brne Mode1
rjmp M0_Start
Mode1:
cpi mode,1 ;external rising Clock, int. Trigger
brne Mode2
rjmp M1_Start
Mode2:
cpi mode,2 ;external falling Clock, int. Trigger
brne Mode3
rjmp M2_Start
Mode3:
cpi mode,3 ;internal Clock, external Trigger=pos
brne Mode4
rjmp M3_Start
Mode4:
cpi mode,4 ;internal Clock, external Trigger=neg
brne Mode5
rjmp M4_Start
Mode5:
cpi mode,5 ;State
brne Test1
rjmp M5_Start
Test1:
cpi mode,7 ;Binary-Counter
brne Test2
rjmp T1_Start
Test2:
cpi mode,8 ;AA-55-Pattern
brne Test3
rjmp T2_Start
Test3:
cpi mode,9 ;Walking-Zero (Periode=9Takte)
brne M0_Start
rjmp T3_Start
M0_Start:
;-------------------------------------------------------------------
;MODE=0 internal Clock, internal Trigger
;-------------------------------------------------------------------
;Timer-0 initialisieren
mov timereg,delta ;取样间隔
out TCCR0,prescal ;Timer-0 装入分频值并启动
in temp,TCNT0
M0_synchronisieren:
in wreg,TCNT0 ;da Prescaler-Stand unbekannt, auf Timer-
cp wreg,temp ;sprung synchronisieren
breq M0_synchronisieren
ldi wreg,0x00 ;Clear timer-0
out TCNT0,wreg
M0_WaitForTrigger:
M0_TimingLoop1:
in wreg,TCNT0
cp timereg,wreg ;等待，知道到达取样间隔
brne M0_TimingLoop1
add timereg,delta ;下一计数器目标值
sbi PORTD,sample
cbi PORTD,sample ; ___/'''\___ 锁存外部数据
nop
in wreg,PINB ;sample auf triggerung pruefen
or wreg,mask ;
out PORTD,store1 ; 写入SRAM
out PORTD,store2
cpse wreg,trig ;sample = triggerbyte ?
rjmp M0_WaitForTrigger ;nein..
M0_GetSamples: ; 被触发
M0_TimingLoop2:
in wreg,TCNT0
cp timereg,wreg
brne M0_TimingLoop2
add timereg,delta
sbi PORTD,sample ;sample nehmen und
cbi PORTD,sample ;register auf BUS legen
nop
out PORTD,store1
out PORTD,store2
add bufcntL,aux1 ;incr. BufferCounter
adc bufcntH,aux0 ;"
brcc M0_GetSamples
rjmp RAMFull
M3_Start:
;-------------------------------------------------------------------
;MODE=3 internal Clock, externe positive Triggerflanke
;-------------------------------------------------------------------
out TCCR0,prescal ;Timer-0 mit passendem PreScaler verbinden
M3_WaitForTrigger:
M3_TriggerLoop1:
sbi PORTD,sample
cbi PORTD,sample
nop
sbic PINB,extpin ;warte auf triggerpin=L
rjmp M3_TriggerLoop1
M3_TriggerLoop2:
sbi PORTD,sample
cbi PORTD,sample
nop
sbis PINB,extpin ;warte auf triggerpin=H
rjmp M3_TriggerLoop2
in timereg,TCNT0 ;timer einlesen
add timereg,delta ;naechsten samplezeitpunkt berechnen
out PORTD,store1
out PORTD,store2
rjmp M0_GetSamples ;
M4_Start:
;-------------------------------------------------------------------
;MODE=4 internal Clock, externe negative Triggerflanke
;-------------------------------------------------------------------
out TCCR0,prescal ;Timer-0 mit passendem PreScaler verbinden
M4_WaitForTrigger:
M4_TriggerLoop1:
sbi PORTD,sample
cbi PORTD,sample
nop
sbis PINB,extpin ;warte auf triggerpin=H
rjmp M4_TriggerLoop1
M4_TriggerLoop2:
sbi PORTD,sample
cbi PORTD,sample
nop
sbic PINB,extpin ;warte auf triggerpin=L
rjmp M4_TriggerLoop2
in timereg,TCNT0 ;timer einlesen
add timereg,delta ;naechsten samplezeitpunkt berechnen
out PORTD,store1
out PORTD,store2
rjmp M0_GetSamples ;
M1_Start:
;-------------------------------------------------------------------
;MODE=1 external Clock, rising Edge
;-------------------------------------------------------------------
M1_WaitForTrigger:
M1_ClockLoop1:
sbi PORTD,sample
cbi PORTD,sample
nop
sbic PINB,extpin ;warte auf clockpin=L
rjmp M1_ClockLoop1
M1_ClockLoop2:
sbi PORTD,sample
cbi PORTD,sample
nop
sbis PINB,extpin ;warte auf clockpin=H
rjmp M1_ClockLoop2
in wreg,PINB ;sample auf triggerung pruefen
or wreg,mask ;
out PORTD,store1
out PORTD,store2
cpse wreg,trig ;war sample=triggerbyte?
rjmp M1_WaitForTrigger ;nein..
M1_GetSamples:
M1_ClockLoop3:
sbi PORTD,sample
cbi PORTD,sample
nop
sbic PINB,extpin ;warte auf clockpin=L
rjmp M1_ClockLoop3
M1_ClockLoop4:
sbi PORTD,sample
cbi PORTD,sample
nop
sbis PINB,extpin ;warte auf clockpin=H
rjmp M1_ClockLoop4
out PORTD,store1
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