avr

使用MEGA88制作电表的程序

TCNT1
OCR1A
TC1ext
MAX ($FFFF)
MAX
0 1
TC1extREM
TC1extTOP
MAX ($FFFF)
TC1extTOP+1 0
MAX ($FFFF)
OC1A
(EP)
For each energy pulse emitted, an internal pulse counter is increased. When the
counter reaches a given threshold a display pulse sequence is initiated, as shown in
Figure 8. The threshold can be set using calibration coefficients.
Figure 8. Generation of Display Pulses.
OC1A
(EP)
Display
Counter
PD6
(DPP)
PD7
(DPN)
tDPX tDPX tDPX
tDP
N 1 0 1 0 N-1 N
Pulse width and spacing, tDPX, are firmware constants, which are easy to alter. The
default setting generates 100ms long pulses.
The firmware calculates RMS (Root-Mean-Square) values of voltage and currents. An
RMS value is defined as the square root of the mean value of the squares of the
instantaneous values of a periodically varying quantity, averaged over one complete
cycle. The discrete time equation for calculating voltage RMS is as follows:
Display Pulse Outputs
Voltage and Current
Measurement
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Equation 17. Voltage RMS Calculation in Discrete Time Domain.
( )
N
n u
N n
∑?
= =
1 0
2
RMS U
Current RMS is calculated using the same equation, only substituting voltage
samples, u(n), for current samples, i(n).
Accumulated data is stored 32 bits wide (signed long) and the calculation result is
stored as a floating-point number. When properly calibrated, the resulting voltage
measurement is in units of volts and current measurements in units of amperes.
A tamper condition enters when meter wiring is altered in a pilfering manner, typically
with the intention to reduce electricity billing. The firmware detects, signals and
continues to measure accurately under more than twenty known tamper conditions,
including reversal of current and partial or whole earth reroutings.
Tamper detection is based on monitoring current flow in both live and neutral wires.
Tamper indicators are set if any inconsistency is detected between the two currents.
Actions are then taken to ensure measurement data is recorded correctly, regardless
of the type of pilfering attempt.
An earth fault means some or all loads have been connected to another ground
potential and not the neutral wire. A partial earth fault is illustrated in Figure 9. Full
current, ITOT, only flows through one of the current transformers, since part of the
return current, I2, does not go through the meter. As a consequence, the current in
the neutral wire, I1, is less than that in the live wire, ITOT. Alternatively, if live and
neutral wires have been swapped, the current in the live wire is less than that in the
neutral.
Figure 9. Partial Earth Fault.
L N
RL1
RL1
ITOT
I1
I2
METER
LOAD
The firmware constantly monitors current flow in both wires and signals an earth fault
if the magnitude difference between the two exceeds a given a threshold. The
threshold has been hardwired to 5%, but is easily adjusted in the source code.
Tamper Detection
Earth Fault
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The earth fault indicator is set during initialization and will not be cleared until at least
one set of valid readings have been found. This means that if the meter is powered
on at a no-load condition the fail indicator will remain constantly set.
The firmware always uses the larger of the two readings for driving the energy pulse
and an earth fault therefore has no effect on the accuracy.
A reversed current condition means current in one or both wires is flowing in the
wrong direction. As a consequence, active power readings will have the wrong sign.
The firmware activates the reversed current indicator when any of the two currents
has a sign opposite the one expected. Figure 10 illustrates how return current, I2, has
been reversed while live current, I1, flows in the expected direction.
Figure 10. Reversed Return Current.
L N
RL
I1
METER
LOAD
I2
The reversed current indicator is set during initialization, but is soon cleared, provided
currents in live and neutral wires flow in the correct direction.
The firmware always uses the absolute value of active power for driving the energy
pulse and the direction of current therefore has no effect on accuracy.
No two meters are alike and individual variations are to be expected. Typical
tolerance figures for components used in the meter are 5%, which means the
assembled meter has an inherent error of the same magnitude. Hence, each meter
must be calibrated before accurate measurement result can be obtained.
Rather than populating the meter with trimming resistors and rely on slow, manual
calibration the procedure is readily carried out in the digital domain. Calibration
coefficients are first calculated for each meter individually, then stored in on-chip
EEPROM and later retrieved during firmware initialization. The coefficients trim the
calculations such that measurement results are accurate within limits.
Digital calibration is accurate and efficient, it is quick to perform, requires little or no
manual intervention, and does not degrade over time. In addition, calibration data is
safely stored in the internal EEPROM.
Phase displacements between signals are introduced by current transformers, input
filters and by the multiplexing of input channels. Some DC immune transformers may
well introduce phase displacements of more than 5 degrees while the multiplexing
introduces a time difference between all channels, inversely proportional to the
sampling frequency. At approximately 2400Hz sampling frequency, the time delay is
1/2400Hz = 0.42ms, which means that at 50Hz mains frequency there is a phase
difference of 360 x (50Hz/2400Hz) = 7.5 degrees.
Reversed Current
Calibration
Phase
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The phase displacements are adjusted using linear interpolation, which is fast, easy
and sufficiently accurate. The limitation is that linear interpolation introduces a
constant time delay to the signal, which means phase can be correctly adjusted for
one frequency, only. Signal components above mains frequency, i.e. harmonics,
cannot be simultaneously phase-adjusted using this approach. Typically, though, this
is not a problem since most of the signal energy lies in the first harmonic.
The algorithm uses two subsequent samples to interpolate an intermediate point. This
means that the higher the sampling frequency, the lower the phase adjustment
margin. At approximately 2400Hz sampling rate (800Hz per channel) and 50Hz mains
frequency, the highest phase delay that can be interpolated is 360 x (50Hz/800Hz) =
22.5 degrees.
The effect of the phase calibration coefficients is shown in the following equation.
Equation 18. Effect of Phase Calibration Coefficient.
CLK
M
f
3 13 128 f 360
65536
PCC Z
× × × × °
× =
Here PCC is the phase calibration coefficient, fM is the mains frequency and fCLK the
system clock frequency. There is one phase calibration coefficient for each input
channel, i.e. three in total. Note, that the 16-bit phase calibration coefficients are
treated unsigned.
Magnitude errors are introduced to all measurement results due to variations in
discrete component values, but are easily corrected using a set of gain calibration
coefficients. There are separate gain coefficients for voltage and each amplification
range of both current channels, i.e. 1 + 2 x 3 = 7 in total.
Current samples are filtered, phase adjusted and then accumulated. For active power
calculations, the current samples are first multiplied with voltage samples and then
accumulated. At the end of each calculation cycle all accumulation registers are
normalized and the results are then multiplied with corresponding gain coefficients.
For each current channel, one of three gain coefficients is used, depending on the
amplifier setting, i.e. different coefficients are used at low, medium and high
amplification.
The effect of current gain coefficients is shown in the following equation.
Equation 19. Effect of Current Gain Coefficients.
N
CAL IG
I I =
Here IG is the current gain coefficient and N denotes amplifier setting (N=1,2,3). The
same equation holds for both live and neutral current measurements.
The 16-bit coefficients are treated unsigned.
Assume meter is configured for 10A maximum current. At full-scale, sinusoidal input
and lowest amplifier setting the peak-to-peak value of sampled data is 1023. After
prescaling (x32) and DC removal, the amplitude of the sampled signal is:
Current Gain
Example
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Equation 20. Amplitude After HPF.
130432
2
1023 255 i? ± =
×
=
After scaling (1/64) and taking the square of each sample, the amplitude is now +/-
4153444. At 4MHz system clock, 128 ADC prescaler and 50Hz mains there are
16.026 samples per mains cycle. Accumulating over 25 x 16.026 = 401 samples,
normalizing and taking the square root, the result before calibration is:
Equation 21. Result Before Calibration.
755 . 1713
2 401
4143444 401 I =
×
×
=
Dividing the result with a calibration coefficient of 1713.755 / 10 = 171.3755 the result
is:
Equation 22. Result After Calibration.
000 . 10
171.3755
1713.755 ICAL = =
Voltage is calibrated similarly as current, but since gain remains constant only one
coefficient is required. The effect of the voltage gain coefficient, UG, is shown in the
following equation.
Equation 23. Effect of Voltage Gain Coefficient.
65536
UG U UCAL
×
=
The 16-bit gain coefficient is treated unsigned.
Active power measurements do not require a dedicated gain coefficient, but use
current and voltage gain coefficients. Measurement results are multiplied with the
voltage coefficient and the corresponding current coefficient. The effect is shown in
the following equation.
Equation 24. Effect of Voltage and Current Gain Coefficients on Active Power.
N
CAL IG UG
P P
×
=
The meter constant dictates the relationship between amount of active power
measured and the frequency of the Energy Pulse output. The larger the active power,
the higher the frequency, fEP, as illustrated in the equation below.
Equation 25. Effect of Meter Constant.
000 600 3
MC P fEP
×
=
Voltage Gain
Active Power Gain
Meter Constant
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Here P is active power in watts and MC is the meter constant in impulses/kilowatthour.
Note, that the pulse frequency also depends on the system clock. The above
equation assumes a system clock of 4MHz.
The calibration coefficient is treated as a 16-bit, unsigned integer.
The Energy Pulse output is typically wired to an LED and used for calibration and
verification purposes. The pulse must be sufficiently long to light the LED for an
optical reader to register it, but also sufficiently short to allow a reasonably high output
frequency. The default is 50ms active time, which limits the frequency to about 10Hz.
At 4MHz system clock, 10A max current and 230V nominal voltage, this means the
maximum meter constant is about 15000 imp/kWh. To increase the meter constant
above this, the maximum current and the pulse length must be decreased.
Another limitation is the quantization of the pulse interval. At default system clock
(4MHz) and default T/C prescaler (1024), the timer is updated once every
1024/4000000 = 0.256ms. Assuming highest default pulse rate (10Hz) the pulse
interval is 100ms and the highest quantization inaccuracy is +/-(0.256/100) = +/-
0.256%. For practical purposes it is recommended to scale system clock, maximum
current and meter constant such that the timer/counter interval never goes below,
say, 500 timer ticks. By default (4MHz, 10A, 230V, 10000imp/kWh) the pulse interval
will not go below 500 ticks.
A pulse pair is provided to drive a stepper-motor counter. Typically, the required
display pulse rate is much lower than the energy pulse rate. The pulse rate, fDP, can
be adjusted using the DPC calibration coefficient, as follows:
Equation 26. Effect of Display Pulse Constant.
DPC
f f EP
DP =
Here fEP is the energy pulse rate. The 16-bit display constant is treated unsigned.
The EEPROM layout of calibration coefficients is shown in the table below. All
coefficients are 16-bit wide and stored with high byte first, then low byte.
Table 6. Calibration Coefficient Layout in EEPROM.
ADDR. + 0x00 + 0x01 + 0x02 + 0x03 + 0x04 + 0x05 + 0x06 + 0x07
0x00 PCC0 PCC1 PCC2 ILG0
0x08 ILG1 ILG2 ING0 ING1
0x10 ING2 UG MC DPC
0x18 CRCW CRC16
PCC is the phase calibration coefficient and ILG and ING are the current gain
coefficients for live and neutral wires, respectivelty. UG is the voltage gain coefficient,
MC the meter constant and DPC the display pulse constant. CRC16 contains the
checksum for the low 32 bytes of the EEPROM. If CRCW is set to to 0x4357 then the
checksum is calculated by the firmware and written to CRC16.
Limitations
Display Constant
Coefficient Layout
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Program constants are values that can be altered before the firmware is compiled, but
not afterwards. Typical constants are various bit and flag definitions, but also included
are some fundamental invariables, such as pulse lengths and sample rates. Some of
the fundamental constants are discussed below.
This constant defines the threshold when to increase amplification of current signal.
Amplification is increased when the amplitude of the filtered current signal drops
below this level. Should be below (255 x 1023) / current gain.
These are low and high levels, which define saturation limits for current samples.
Amplification is decreased when unconditioned current samples go below low limit or
above high limit. Recommended a few LSB’s below max and above min.
This is the number of samples to wait before allowing a new gain switch to take place.
By default, the amplifier settles in a few hundred sampling cycles, which means a
value of 100 should be enough.
Starting current in amperes. Active power readings are cleared when current
measurement drops below this limit. Should be set according to IEC 61036 standard.
Constant offset, which is added to all measurement results. Improves linearity at low
amplitudes, if properly scaled. Should be around ? LSB x 255 = 128.
This is the number of samples to accumulate during each calculation cycle. Large
values create more stable results but at longer intervals. Should be an integral
multiple of number of samples per mains cycle.
This is the inverse of NMAX. It is a pre-calculated constant, which is used at the end
of each accumulation cycle.
This is the length and spacing of display pulses, in units of sampling cycles.
The main program is mostly idle (looping) and is interrupted only when a fresh sample
is available from the ADC or when the timer/counter requires service. The most
frequently occurring event is the ADC interrupt service, which must be complete
before the next service request arrives. In order to monitor that the ADC ISR does not
consume too many instructions cycles the service routine sets and clears a pulse
upon entry and exit, respectively.
By default, the duty cycle pulse is routed to the lowest bit of port B. The duty cycle is
readily monitored with an oscilloscope connected to PB0. The closer the duty cycle is
to 100%, the higher is the risk that there will not be enough clock cycles to process all
data. A conservative duty cycle is below 50%.
Program Constants
AMP_LO
SAT_LO, SAT_HI
GAIN_HOLD
I_MIN
OFFSET
NMAX
NORM
DP_ON
Duty Cycle
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