📄 fenetpq2.c
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switch(FCCx)
{
case FCC2:
IMM->cpm_mux_cmxfcr = 0x00250000;
break;
case FCC3:
IMM->cpm_mux_cmxfcr = 0x00003700;
break;
default:
while (1)
FlashLed(); /* spin here if not FCC2/FCC3 */
};
}
/*--------------------------------------------*/
/* Connect FCCx's Tx and Rx clocks to BRG5 */
/* if in internal loopback mode. */
/*--------------------------------------------*/
else
{
IMM->cpm_mux_cmxfcr = ALL_ZEROS;
IMM->cpm_mux_cmxuar = ALL_ZEROS;
IMM->clocks_sccr &= 0xFFFFFFFC;
IMM->brgs_brgc5 = 0x00010006;
}
/********************************************/
/* Common Parameter RAM Area Initialization */
/********************************************/
IMM->pram.serials.fcc_pram[FCCx].riptr = 0x3000;
IMM->pram.serials.fcc_pram[FCCx].tiptr = 0xb000;
/*------------------------------------------*/
/* Let FCCx know where base of RxBDs are */
/*------------------------------------------*/
IMM->pram.serials.fcc_pram[FCCx].rbase = (UWORD)&RxTxBD->RxBD[0];
/*------------------------------------------*/
/* Let FCCx know where base of TxBDs are */
/*------------------------------------------*/
IMM->pram.serials.fcc_pram[FCCx].tbase = (UWORD)&RxTxBD->TxBD[0];
/*-----------------------------------------------------------------*/
/* Set RFCR,TFCR -- Rx,Tx Function Code */
/* */
/* Note that the Function code registers reside in the upper byte */
/* of RSTATE and TSTATE */
/*-----------------------------------------------------------------*/
/* Mot byte ordering, Buffers and BDs on 60x bus */
IMM->pram.serials.fcc_pram[FCCx].rstate &= 0x00FFFFFF;
IMM->pram.serials.fcc_pram[FCCx].rstate |= 0x10000000;
/* Mot byte ordering, Buffers and BDs on 60x bus */
IMM->pram.serials.fcc_pram[FCCx].tstate &= 0x00FFFFFF;
IMM->pram.serials.fcc_pram[FCCx].tstate |= 0x10000000;
/*-----------------------------------------------*/
/* Set MRBLR -- Max. Receive Buffer Length */
/* Must be divisible by 32 and not less than 64. */
/*-----------------------------------------------*/
IMM->pram.serials.fcc_pram[FCCx].mrblr = ENET_MRBLR;
/**************************************************/
/* Ethernet Specific Parameter RAM Initialization */
/**************************************************/
/* set up abbreviated pointer */
FCCxEthernet =
(t_EnetFcc_Pram * ) &(IMM->pram.serials.fcc_pram[FCCx].SpecificProtocol.e);
FCCxEthernet->c_mask = ENET_C_MASK; /* Constant MASK for CRC */
FCCxEthernet->c_pres = ENET_C_PRES; /* CRC Preset */
FCCxEthernet->crcec = ALL_ZEROS; /* CRC Error Counter */
FCCxEthernet->alec = ALL_ZEROS; /* Align. Error Counter */
FCCxEthernet->disfc = ALL_ZEROS; /* Discard Frame Counter */
FCCxEthernet->ret_lim = ENET_RET_LIM; /* Retry Limit Threshold */
FCCxEthernet->p_per = ALL_ZEROS; /* Persistence */
FCCxEthernet->gaddr_h = ALL_ZEROS; /* Group Addr. Filter 1 */
FCCxEthernet->gaddr_l = ALL_ZEROS; /* Group Addr. Filter 2 */
FCCxEthernet->tfcstat = ALL_ZEROS; /* temp BD holder */
FCCxEthernet->mflr = ENET_MFLR; /* Max Frame Length Reg. */
FCCxEthernet->paddr1_h = ENET_PADDR_H; /* Phys. Addr. 1 (MSB) */
FCCxEthernet->paddr1_m = ENET_PADDR; /* Phys. Addr. 1 */
FCCxEthernet->paddr1_l = ENET_PADDR_L; /* Phys. Addr. 1 (LSB) */
FCCxEthernet->iaddr_h = ALL_ZEROS; /* Ind. Addr. Filter 1 */
FCCxEthernet->iaddr_l = ALL_ZEROS; /* Ind. Addr. Filter 2 */
FCCxEthernet->minflr = ENET_MINFLR; /* Min Frame Length Reg. */
FCCxEthernet->taddr_h = ALL_ZEROS; /* Temp Address (MSB) */
FCCxEthernet->taddr_m = ALL_ZEROS; /* Temp Address */
FCCxEthernet->taddr_l = ALL_ZEROS; /* Temp Address (LSB) */
FCCxEthernet->pad_ptr =
IMM->pram.serials.fcc_pram[FCCx].tiptr;/* internal pad pointer, can be
same as TIPTR if no specific
character needed. */
FCCxEthernet->cf_type = ALL_ZEROS; /* reserved, cleared */
FCCxEthernet->maxd1 = ENET_MDMA; /* Max DMA1 Length Reg. */
FCCxEthernet->maxd2 = ENET_MDMA; /* Max DMA2 Length Reg. */
/****************************/
/* Register Initializations */
/****************************/
/*---------------------------------*/
/* Initialize GFMR: */
/* */
/* MODE = 1100 (ethernet) */
/*---------------------------------*/
IMM->fcc_regs[FCCx].gfmr = 0x0000000C;
if (loopback == INTERNAL)
IMM->fcc_regs[FCCx].gfmr |= 0x60000000; /* DIAG=01 (Local Loopback Mode), TCI = 1 */
/*-------------------*/
/* Set DSR to 0xD555 */
/*-------------------*/
IMM->fcc_regs[FCCx].dsr = ENET_DSR;
/*------------------------------------------------*/
/* Initialize PSMR: */
/* */
/* LPB=1, FDE=1, CRC = 10 (32-bit) */
/*------------------------------------------------*/
if (Interface == RMII)
IMM->fcc_regs[FCCx].psmr = 0x14020080; /* RMII Interafce mode */
else
IMM->fcc_regs[FCCx].psmr = 0x14000080; /* MII Interafce mode */
/*-----------------------------------------*/
/* Clear FCCE Register by writing all 1's. */
/*-----------------------------------------*/
IMM->fcc_regs[FCCx].fcce = 0xFFFF0000;
/*-----------------------------------------------------------------*/
/* Issue Init RX & TX Parameters Command for FCCx. This command to */
/* the CR lets it know to reinitialize FCCx with the new parameter */
/* RAM values. When the ENT/ENR bits are set below, Hunt Mode will */
/* begin automatically. */
/*-----------------------------------------------------------------*/
while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD)
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
(CPCR_PAGE_FCC1|(FCCx << 26)) |
(CPCR_SBC_FCC1|(FCCx << 21)) |
CPCR_MCN_FEC |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD)
/*-------------------------------------------------------------*/
/* Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive */
/*-------------------------------------------------------------*/
IMM->fcc_regs[FCCx].gfmr |= GFMR_ENR | GFMR_ENT;
}/* end FCCxInit() */
/*--------------------------------------------------------------------------
*
* FUNCTION NAME: ExtIntHandler
*
* DESCRIPTION:
*
* Process External Interrupt (assumes only interrupts from FCCx)
*
* Main Processing Steps:
*
* (1) Test input vector against External Interrupt Vector.
*
* (2) Test Interrupt Code in SIU Interrupt Vector Reg (SIVEC) against
* FCCx
*
* (3) Save off FCCE for FCCx (FCCx Event Register)
*
* (4) Clear FCCx Event Register
*
* (5) Process FCCx event
*
*
* NOTE: This ISR will only handle ONE RX event. This interrupt happens
* when the last frame of eight is received.
*
* EXTERNAL EFFECTS: interrupt related registers
*
* PARAMETERS:
*
* vector - interrupt vector (address)
*
* RETURNS: NONE
*
*-------------------------------------------------------------------------*/
void ExtIntHandler(UWORD vector)
{
UWORD ic_sivec;
UWORD fcce;
UHWORD index = 0;
/*------------------------------------*/
/* Shift the 5-bit interrupt code */
/* down to the least significant bits */
/*------------------------------------*/
ic_sivec = IMM->ic_sivec >> 26; /* sivec interrupt code */
/*-------------------------------------*/
/* Match input vector against External */
/* Interrupt Vector -- 0x500 on PPC */
/*-------------------------------------*/
if (vector != EXT_INT_VECTOR) /* interrupt NOT external to core */
{
while (1)
FlashLed(); /* spin here if error is flagged */
};
/*--------------------------------*/
/* Match event against FCC2 value */
/*--------------------------------*/
if (ic_sivec != (SIVEC_FCC1|(1*FCCx))) /* interrupt NOT from FCCx */
{
while (1)
FlashLed(); /* spin here if error is flagged */
};
/*-----------------------------*/
/* Copy the FCC event register */
/*-----------------------------*/
fcce = IMM->fcc_regs[FCCx].fcce; /* Save off scce */
/*-------------------------------------------*/
/* Clear FCCx Event Register (by writing 1s) */
/*-------------------------------------------*/
IMM->fcc_regs[FCCx].fcce = 0xFFFF0000;
/*-------------------------------------------------------------*/
/* Process FCC Ethernet Event if the event flag for RXF is set */
/*-------------------------------------------------------------*/
if (fcce & 0x00080000)
{
/*--------------------------------------------*/
/* Traverse through available Receive Buffers */
/* to locate first filled buffer. */
/*--------------------------------------------*/
while ((!BDEmpty(RxTxBD->RxBD[index].bd_cstatus) &&
(index < NUM_RXBDS)))
{
/*---------------------------------------*/
/* Compare the receive buffer with its */
/* corresponding transmit buffer. */
/*---------------------------------------*/
if (memcmp(&BufferPool[index],
&BufferPool[index+FIRST_TX_BUF],
(BUFFER_SIZE-4)))
{
RxGood=FALSE; /* they didn't compare */
}
/*-----------------------------------------------------------*/
/* In this architecture, every frame encompasses a buffer */
/* descriptor's worth of data. This a very simple example. */
/* Normally there could be several BD's in a frame, and once */
/* a data buffer was processed, it could be released for */
/* use. */
/* */
/* Although not invoked in this example, lines to that */
/* are included here for the user's benefit, and to */
/* represent where BD handling could occur in a more */
/* complete handler. */
/* */
/* In this example, EVERY BD is the first and last BD in */
/* frame, so the following IF will not test true in this */
/* example. */
/*-----------------------------------------------------------*/
if(!LastBD(RxTxBD->RxBD[index].bd_cstatus ))
{
RxTxBD->RxBD[index].bd_cstatus |= 0x8000; /* set empty flag */
/*-------------------------------------*/
/* checking all status bits for errors */
/*-------------------------------------*/
if (BDRxError(RxTxBD->RxBD[index].bd_cstatus ))
RxGood = FALSE;
}
/*------------------------------------------*/
/* Again, the following line is included */
/* merely as an example. */
/* */
/* This is the last BD in the chain. Clear */
/* all bits but the Ready bit and Wrap bit. */
/*------------------------------------------*/
/* if (index == (NUM_RXBDS-1))
RxTxBD->RxBD[index].bd_cstatus = 0xA000; */
/*------------------------------------*/
/* Set RX process index to start next */
/* BD scan from the BD after this one */
/*------------------------------------*/
RxProcIndex = index+ 1;
if (RxProcIndex == 8)
NotDone=FALSE;
index++;
}
}
else
RxGood = FALSE; /* Expected to see RXF event in FCCE */
/*-------------------------------------*/
/* Here's our error loop. Spin here */
/* indefinitely if there was an error. */
/*-------------------------------------*/
if (RxGood == FALSE)
{
Led(GREEN);
while (1); /* spin here if error is flagged */
};
} /* end ExtIntHandler */
/*--------------------------------------------------------------------------
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