tmdlao.c

Nexperia系统声音实现的源码

    *rGain = vol[1];

    return TM_OK;
}
/**************************************************************************************/
extern tmErrorCode_t tmdlAoSetSampleRate(Int instance, Float sRate)
{

    DBG_ISR_PRINT((DBG_UNIT_NAME, DBG_LEVEL_1,"Entered tmdlAoSetSampleRate(%x,%f)\n", instance, sRate));
    tmAssert (instance, TMDL_ERR_AO_NOT_OWNER);
    return tmdlAoInstanceConfig(instance, TMDL_CMD_AO_SET_SAMPLERATE, (Pointer)&sRate);
}
/**************************************************************************************/
extern tmErrorCode_t tmdlAoGetSampleRate(Int instance, Float *sRate)
{

    DBG_PRINT((DBG_UNIT_NAME, DBG_LEVEL_1,"Entered tmdlAoGetSampleRate(%x,%x)\n", instance, sRate));
    tmAssert (instance, TMDL_ERR_AO_NOT_OWNER);
    return tmdlAoInstanceConfig(instance, TMDL_CMD_AO_GET_SAMPLERATE, (Pointer)sRate);
}
/**************************************************************************************/
extern tmErrorCode_t tmdlAoSetIntState(Int instance, Bool enable)
{
    DBG_PRINT((DBG_UNIT_NAME, DBG_LEVEL_1,"Entered tmdlAoSetIntState(%x,%d)\n",instance, enable));
    tmAssert (instance, TMDL_ERR_AO_NOT_OWNER);
    return tmdlAoInstanceConfig(instance, TMDL_CMD_AO_INT_STATE, (Pointer)enable);
}
/**************************************************************************************/
extern tmErrorCode_t tmdlAoGetCapabilities(ptmdlAoCapabilities_t *pCap)
{
    DBG_ATTACH_MODULE(DBG_UNIT_NAME, DBG_UNIT_STR, DBG_PREREGISTER);
    DBG_PRINT((DBG_UNIT_NAME, DBG_LEVEL_1,"Entered tmdlAoGetCapabilities(%x)\n", pCap));
    return tmdlAoGetCapabilitiesM(pCap, tmUnit0);
}
/**************************************************************************************/
extern tmErrorCode_t tmdlAoOpen(Int *instance)
{
    DBG_ATTACH_MODULE(DBG_UNIT_NAME, DBG_UNIT_STR, DBG_PREREGISTER);
    DBG_PRINT((DBG_UNIT_NAME, DBG_LEVEL_1,"Entered tmdlAoOpen(%x)\n", instance));
    return tmdlAoOpenM(instance, tmUnit0);
}

/**************************************************************************************/
static tmErrorCode_t
aoSetClock(
     tmUnitSelect_t unitName,
     UInt32         mmioBase,
     Float          fOsclk,
     UInt32         cpuFreq
     )
{
#if   (TMFL_PNX_ID == 8525)   // PNX8525/Viper1

#define AO1_MMIOBASE        0x110000
#define AO2_MMIOBASE        0x112000
#define AIO3_MMIOBASE       0x114000
#define DDS_AO1_CTL         0x04710C
#define DDS_AO2_CTL         0x047114
#define DDS_AIO3_CTL        0x047118
#define AO1_OSCLK_CTL       0x047314
#define AO2_OSCLK_CTL       0x04731C
#define AIO3_OSCLK_CTL      0x047320
#define CLK_AO1_SCK_O_CTL   0x047430
#define CLK_AO2_SCK_O_CTL   0x047438
#define CLK_AIO3_SCK_O_CTL  0x04743C
    switch(mmioBase)
    {
       case AO1_MMIOBASE :
           /* clock module register setup for AO unit 0*/
           /* fOsclk * (2e32))/ (1.728 * (10e9))); */
           MMIO(DDS_AO1_CTL)      = (UInt32) (2.4855134815*fOsclk);
           /* enable OSCLK to functional clock */
           MMIO(AO1_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           MMIO(CLK_AO1_SCK_O_CTL) = 0x3;
           break;
       case AO2_MMIOBASE :
           /* clock module register setup for AO unit 1*/
           /* fOsclk * (2e32))/ (1.728 * (10e9))); */
           MMIO(DDS_AO2_CTL)      = (UInt32) (2.4855134815*fOsclk);
           /* enable OSCLK to functional clock */
           MMIO(AO2_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           MMIO(CLK_AO2_SCK_O_CTL) = 0x3;
           break;
       case AIO3_MMIOBASE :
           /* clock module register setup for AO unit 2*/
           /* fOsclk * (2e32))/ (1.728 * (10e9))); */
           MMIO(DDS_AIO3_CTL)      = (UInt32) (2.4855134815*fOsclk);
           /* enable OSCLK to functional clock */
           MMIO(AIO3_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           MMIO(CLK_AIO3_SCK_O_CTL) = 0x3;
           break;

       default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }

#elif   (TMFL_PNX_ID == 8550)   // PNX8550/Viper2

#define AO1_MMIOBASE        0x110000
#define AO2_MMIOBASE        0x112000
#define DDS_AO1_CTL         0x04702C
#define DDS_AO2_CTL         0x047034
#define AO1_OSCLK_CTL       0x047B08
#define AO2_OSCLK_CTL       0x047B10
#define CLK_AO1_SCK_O_CTL   0x047B1C
#define CLK_AO2_SCK_O_CTL   0x047B24

    switch(mmioBase)
    {
       case AO1_MMIOBASE :
           /* clock module register setup for AO unit 0*/
           /* fOsclk * (2e32))/ (1.728 * (10e9))); */
           MMIO(DDS_AO1_CTL)      = ((UInt32) (2.4855134815*fOsclk))& 0x7FFFFFFF;
           /* enable OSCLK to functional clock */
           if( MMIO(AO1_OSCLK_CTL) != 0x3 ) MMIO(AO1_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           if( MMIO(CLK_AO1_SCK_O_CTL) != 0x3 ) MMIO(CLK_AO1_SCK_O_CTL) = 0x3;
           break;
       case AO2_MMIOBASE :
           /* clock module register setup for AO unit 1*/
           /* fOsclk * (2e32))/ (1.728 * (10e9))); */
           MMIO(DDS_AO2_CTL)      = ((UInt32) (2.4855134815*fOsclk))& 0x7FFFFFFF;
           /* enable OSCLK to functional clock */
           if( MMIO(AO2_OSCLK_CTL) != 0x3 ) MMIO(AO2_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           if( MMIO(CLK_AO2_SCK_O_CTL) != 0x3 ) MMIO(CLK_AO2_SCK_O_CTL) = 0x3;
           break;

       default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }
#elif   (TMFL_PNX_ID == 1300)   // PNX1300/TM1300

    aoSetFREQM(mmioBase, ((UInt) (2147483648.0+ (Float)(477218588.4 * fOsclk)

#elif   (TMFL_PNX_ID == 1500)   // PNX1500/TM1500
#define AO1_MMIOBASE        0x110000
#define DDS_AO1_CTL         0x04701C
#define AO1_OSCLK_CTL       0x047308
#define CLK_AO1_SCK_O_CTL   0x04730C

    switch(mmioBase)
    {
       case AO1_MMIOBASE :
           /* clock module register setup for AO unit 0*/
           /* fOsclk * (2e32))/ (1.728 * (10e9))); */
           MMIO(DDS_AO1_CTL)      = (((UInt32) (2.4855134815*fOsclk))& 0x7FFFFFFF)|0x80000000;
           /* enable OSCLK to functional clock */
           /*if( MMIO(AO1_OSCLK_CTL) != 0x3 )*/ MMIO(AO1_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           /*if( MMIO(CLK_AO1_SCK_O_CTL) != 0x3 )*/ MMIO(CLK_AO1_SCK_O_CTL) = 0x3;
           break;
       default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }

#else

#error  ERROR: TMFL_PNX_ID Nexperia chip ID not defined !

#endif

    return TM_OK;
}

/**************************************************************************************/
static tmErrorCode_t
aoGetClock(
     tmUnitSelect_t unitName,
     UInt32         mmioBase,
     Float          *fOsclk,
     UInt32         cpuFreq
     )
{
     UInt32                 clockBase =0;
#if   (TMFL_PNX_ID == 8525)   // PNX8525/Viper1

    switch(mmioBase)
    {
         case AO1_MMIOBASE : clockBase = DDS_AO1_CTL; break;
         case AO2_MMIOBASE : clockBase = DDS_AO2_CTL; break;
         case AIO3_MMIOBASE : clockBase = DDS_AIO3_CTL; break;
         default:     return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }
    /* clock module register value for AO unit */
    /*[{(1.728 * 10e9)/(2e32)} * N];*/
    *fOsclk =  (Float) (0.402331*MMIO (clockBase));

#elif   (TMFL_PNX_ID == 8550)   // PNX8550/Viper2
    switch(mmioBase)
    {
         case AO1_MMIOBASE : clockBase = DDS_AO1_CTL; break;
         case AO2_MMIOBASE : clockBase = DDS_AO2_CTL; break;
         default:     return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }
    /* clock module register value for AO unit */
    /*[{(1.728 * 10e9)/(2e32)} * N];*/
    *fOsclk =  (Float) (0.402331*MMIO (clockBase));

#elif   (TMFL_PNX_ID == 1300)   // PNX1300/TM1300

    *fOsclk = (Float) ((aoGetFREQM (mmioBase) - 2147483648.0)*
                      ((Float)cpuFreq/477218588.4));

#elif   (TMFL_PNX_ID == 1500)   // PNX1500/TM1500

    switch(mmioBase)
    {
      case AO1_MMIOBASE : clockBase = DDS_AO1_CTL; break;
      default:   return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }
    /* clock module register value for AO unit */
    /*[{(1.728 * 10e9)/(2e32)} * N];*/
    *fOsclk =  (Float) (0.402331*(MMIO (clockBase)& 0x7FFFFFFF));

#else

#error  ERROR: TMFL_PNX_ID Nexperia chip ID not defined !

#endif
    return TM_OK;

}

/**************************************************************************************/
/* Description: Select system (27 MHz) clock source */
static tmErrorCode_t
aoResetClock(
     tmUnitSelect_t unitName,
     UInt32         mmioBase
     )
{
#if   (TMFL_PNX_ID == 8525)   // PNX8525/Viper1

    switch(mmioBase)
    {
       case AO1_MMIOBASE :
           /* enable OSCLK to functional clock */
           MMIO(AO1_OSCLK_CTL)     = 0x1;
           /* enable SCK to functional clock */
           MMIO(CLK_AO1_SCK_O_CTL) = 0x1;
           break;
       case AO2_MMIOBASE :
           /* enable OSCLK to functional clock */
           MMIO(AO2_OSCLK_CTL)     = 0x1;
           /* enable SCK to functional clock */
           MMIO(CLK_AO2_SCK_O_CTL) = 0x1;
           break;
       case AIO3_MMIOBASE :
           /* enable OSCLK to functional clock */
           MMIO(AIO3_OSCLK_CTL)     = 0x1;
           /* enable SCK to functional clock */
           MMIO(CLK_AIO3_SCK_O_CTL) = 0x1;
           break;

       default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }

#elif   (TMFL_PNX_ID == 8550)   // PNX8550/Viper2

    switch(mmioBase)
    {
       case AO1_MMIOBASE :
           /* enable OSCLK to functional clock */
           if( MMIO(AO1_OSCLK_CTL) != 0x1 ) MMIO(AO1_OSCLK_CTL)     = 0x1;
           /* enable SCK to functional clock */
           if( MMIO(CLK_AO1_SCK_O_CTL) != 0x1 ) MMIO(CLK_AO1_SCK_O_CTL) = 0x1;
           break;
       case AO2_MMIOBASE :
           /* enable OSCLK to functional clock */
           if( MMIO(AO2_OSCLK_CTL) != 0x1 ) MMIO(AO2_OSCLK_CTL)     = 0x1;
           /* enable SCK to functional clock */
           if( MMIO(CLK_AO2_SCK_O_CTL) != 0x1 ) MMIO(CLK_AO2_SCK_O_CTL) = 0x1;
           break;

       default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }

#elif   (TMFL_PNX_ID == 1300)   // PNX1300/TM1300

#elif   (TMFL_PNX_ID == 1500)   // PNX1500/TM1500

switch(mmioBase)
{
    case AO1_MMIOBASE :
       /* enable OSCLK to functional clock */
       if( MMIO(AO1_OSCLK_CTL) != 0x1 ) MMIO(AO1_OSCLK_CTL)     = 0x1;
       /* enable SCK to functional clock */
       if( MMIO(CLK_AO1_SCK_O_CTL) != 0x1 ) MMIO(CLK_AO1_SCK_O_CTL) = 0x1;
       break;
    default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
}

#endif

    return TM_OK;
}

/**************************************************************************************/
/* Description: Select 90 KHz clock source */
static tmErrorCode_t
aoUnResetClock(
     tmUnitSelect_t unitName,
     UInt32         mmioBase
     )
{
#if   (TMFL_PNX_ID == 8525)   // PNX8525/Viper1

    switch(mmioBase)
    {
       case AO1_MMIOBASE :
           /* enable OSCLK to functional clock */
           MMIO(AO1_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           MMIO(CLK_AO1_SCK_O_CTL) = 0x3;
           break;
       case AO2_MMIOBASE :
           /* enable OSCLK to functional clock */
           MMIO(AO2_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           MMIO(CLK_AO2_SCK_O_CTL) = 0x3;
           break;
       case AIO3_MMIOBASE :
           /* enable OSCLK to functional clock */
           MMIO(AIO3_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           MMIO(CLK_AIO3_SCK_O_CTL) = 0x3;
           break;

       default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }

#elif   (TMFL_PNX_ID == 8550)   // PNX8550/Viper2

    switch(mmioBase)
    {
       case AO1_MMIOBASE :
           /* enable OSCLK to functional clock */
           if( MMIO(AO1_OSCLK_CTL) != 0x3 ) MMIO(AO1_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           if( MMIO(CLK_AO1_SCK_O_CTL) != 0x3 ) MMIO(CLK_AO1_SCK_O_CTL) = 0x3;
           break;
       case AO2_MMIOBASE :
           /* enable OSCLK to functional clock */
           if( MMIO(AO2_OSCLK_CTL) != 0x3 ) MMIO(AO2_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           if( MMIO(CLK_AO2_SCK_O_CTL) != 0x3 ) MMIO(CLK_AO2_SCK_O_CTL) = 0x3;
           break;

       default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }

#elif   (TMFL_PNX_ID == 1300)   // PNX1300/TM1300

#elif   (TMFL_PNX_ID == 1500)   // PNX1500/TM1500

    switch(mmioBase)
    {
        case AO1_MMIOBASE :
           /* enable OSCLK to functional clock */
           if( MMIO(AO1_OSCLK_CTL) != 0x3 ) MMIO(AO1_OSCLK_CTL)     = 0x3;
           /* enable SCK to functional clock */
           if( MMIO(CLK_AO1_SCK_O_CTL) != 0x3 ) MMIO(CLK_AO1_SCK_O_CTL) = 0x3;
           break;
        default:         return TMDL_ERR_AO_UNSUPPORTED_UNIT;
    }

#endif

    return TM_OK;
}