mc68376.h

uCOSII在motorala单片机上的移植

/*****************************************************************************
    NOTE:  All values are offsets from either $7FF000 or $FFF000.
    The base address is determined by the modmap bit in SIM_MCR.
    It should be noted that the modmap bit is a write-once bit.  After a
    reset, it is 1 (indicating $FFF000).  The first write to the SIM_MCR
    register will permanently set the modmap bit.
*****************************************************************************/
#ifndef	_MC68376_H
#define	_MC68376_H

#define ABase       0xFFF000         /* define base address */
/**************************** ADC REGISTERS *********************************/
#define QADCMCR   (volatile short *)(ABase+0x200)  /* ADC Module Config. Reg.(word) */
#define QADCTEST  (volatile short *)(ABase+0x202)  /* Module Test Reg.(word) */
#define QADCINT   (volatile short *)(ABase+0x204)  /* Module Test Reg.(word) */
#define PORTQA    (volatile char *)(ABase+0x206)  /* Port Data Register(word) */
#define PORTQB    (volatile char *)(ABase+0x207)  /* Port Data Register(word) */
#define DDRQA     (volatile short *)(ABase+0x208)  /* Module Test Reg.(word) */
#define QACR0     (volatile short *)(ABase+0x20A)  /* Module Test Reg.(word) */
#define QACR1     (volatile short *)(ABase+0x20C)  /* Module Test Reg.(word) */
#define QACR2     (volatile short *)(ABase+0x20E)  /* Module Test Reg.(word) */
#define QASR      (volatile short *)(ABase+0x210)  /* Module Test Reg.(word) */
/* ADC Right-Justified Unsigned Signed Result Register modified by wzm*/
#define ADC_RJ_URSLT0  (volatile short *)(ABase+0x2B0) /* ADC Result Reg. 0(word) */
#define ADC_RJ_URSLT1  (volatile short *)(ABase+0x2B2) /* ADC Result Reg. 0(word) */
#define ADC_RJ_URSLT2  (volatile short *)(ABase+0x2B4) /* ADC Result Reg. 0(word) */
#define ADC_RJ_URSLT3  (volatile short *)(ABase+0x2B6) /* ADC Result Reg. 0(word) */
#define ADC_RJ_URSLT4  (volatile short *)(ABase+0x2B8) /* ADC Result Reg. 0(word) */
#define ADC_RJ_URSLT5  (volatile short *)(ABase+0x2BA) /* ADC Result Reg. 0(word) */
#define ADC_RJ_URSLT6  (volatile short *)(ABase+0x2BC) /* ADC Result Reg. 0(word) */
#define ADC_RJ_URSLT7  (volatile short *)(ABase+0x2BE) /* ADC Result Reg. 0(word) */
#define ADC_RJ_URSLT8   (volatile short *)(ABase+0x2C0) /* ADC Result Reg. 8(word) */
#define ADC_RJ_URSLT9   (volatile short *)(ABase+0x2C2) /* ADC Result Reg. 9(word) */
#define ADC_RJ_URSLT10  (volatile short *)(ABase+0x2C4) /* ADC Result Reg. 10(word) */
#define ADC_RJ_URSLT11  (volatile short *)(ABase+0x2C6) /* ADC Result Reg. 11(word) */
#define ADC_RJ_URSLT12  (volatile short *)(ABase+0x2C8) /* ADC Result Reg. 12(word) */
#define ADC_RJ_URSLT13  (volatile short *)(ABase+0x2CA) /* ADC Result Reg. 13(word) */
#define ADC_RJ_URSLT14  (volatile short *)(ABase+0x2CC) /* ADC Result Reg. 14(word) */
#define ADC_RJ_URSLT15  (volatile short *)(ABase+0x2CE) /* ADC Result Reg. 15(word) */
#define ADC_RJ_URSLT16  (volatile short *)(ABase+0x2D0) /* ADC Result Reg. 16(word) */
#define ADC_RJ_URSLT17  (volatile short *)(ABase+0x2D2) /* ADC Result Reg. 17(word) */
#define ADC_RJ_URSLT18  (volatile short *)(ABase+0x2D4) /* ADC Result Reg. 18(word) */

/* ADC Left-Justified Signed Result Register modified by wzm*/
#define ADC_LJ_RSLT0  (volatile short *)(ABase+0x330)/* ADC Result Reg. 0(word) */
#define ADC_LJ_RSLT1  (volatile short *)(ABase+0x332)/* ADC Result Reg. 1(word) */
#define ADC_LJ_RSLT2  (volatile short *)(ABase+0x334)/* ADC Result Reg. 2(word) */
#define ADC_LJ_RSLT3  (volatile short *)(ABase+0x336)/* ADC Result Reg. 3(word) */
#define ADC_LJ_RSLT4  (volatile short *)(ABase+0x338)/* ADC Result Reg. 4(word) */
#define ADC_LJ_RSLT5  (volatile short *)(ABase+0x33A)/* ADC Result Reg. 5(word) */
#define ADC_LJ_RSLT6  (volatile short *)(ABase+0x33C)/* ADC Result Reg. 6(word) */
#define ADC_LJ_RSLT7  (volatile short *)(ABase+0x33E)/* ADC Result Reg. 7(word) */
/* ADC Left-Justified Unsigned Result Register */
#define ADC_LJ_URSLT0 (volatile short *)(ABase+0x3B0)/* ADC Result Reg. 0(word) */
#define ADC_LJ_URSLT1 (volatile short *)(ABase+0x3B2)/* ADC Result Reg. 1(word) */
#define ADC_LJ_URSLT2 (volatile short *)(ABase+0x3B4)/* ADC Result Reg. 2(word) */
#define ADC_LJ_URSLT3 (volatile short *)(ABase+0x3B6)/* ADC Result Reg. 3(word) */
#define ADC_LJ_URSLT4 (volatile short *)(ABase+0x3B8)/* ADC Result Reg. 4(word) */
#define ADC_LJ_URSLT5 (volatile short *)(ABase+0x3BA)/* ADC Result Reg. 5(word) */
#define ADC_LJ_URSLT6 (volatile short *)(ABase+0x3BC)/* ADC Result Reg. 6(word) */
#define ADC_LJ_URSLT7 (volatile short *)(ABase+0x3BE)/* ADC Result Reg. 7(word) */
/*   ADC CCW table address  -----added by wzm---- */
#define ADC_CCW0   (volatile short *)(ABase+0x230)  /* ADC CCW table Reg.0  */
#define ADC_CCW1   (volatile short *)(ABase+0x232)  /* ADC CCW table Reg.0  */
#define ADC_CCW2   (volatile short *)(ABase+0x234)  /* ADC CCW table Reg.0  */
#define ADC_CCW3   (volatile short *)(ABase+0x236)  /* ADC CCW table Reg.0  */
#define ADC_CCW4   (volatile short *)(ABase+0x238)  /* ADC CCW table Reg.0  */
#define ADC_CCW5   (volatile short *)(ABase+0x23A)  /* ADC CCW table Reg.0  */
#define ADC_CCW6   (volatile short *)(ABase+0x23C)  /* ADC CCW table Reg.0  */
#define ADC_CCW7   (volatile short *)(ABase+0x23E)  /* ADC CCW table Reg.0  */
#define ADC_CCW16  (volatile short *)(ABase+0x250)  /* ADC CCW 16(word) */
#define ADC_CCW17  (volatile short *)(ABase+0x252)  /* ADC CCW 17(word) */
#define ADC_CCW18  (volatile short *)(ABase+0x254)  /* ADC CCW 18(word) */

/**************************** Flash EEPROM Register *************************/
#define FEE1_MCR    (volatile short *)(ABase+0x800)  /* FEE1(16K) Module Confg.Reg.(FEE1MCR)(word)*/
#define FEE1_TST    (volatile short *)(ABase+0x802)  /* FEE1 Test Reg. (word) */
#define FEE1_BAH    (volatile short *)(ABase+0x804)  /* FEE1 Base Address High Reg. */
#define FEE1_BAL    (volatile short *)(ABase+0x806)  /* FEE1 Base Address High Reg. */
#define FEE1_CR     (volatile short *)(ABase+0x808)  /* FEE1 Control Reg. (word) */
#define FEE1_BS0    (volatile short *)(ABase+0x810)  /* FEE1 Bootstrap word 0 */
#define FEE1_BS1    (volatile short *)(ABase+0x812)  /* FEE1 Bootstrap word 1 */
#define FEE1_BS2    (volatile short *)(ABase+0x814)  /* FEE1 Bootstrap word 2 */
#define FEE1_BS3    (volatile short *)(ABase+0x816)  /* FEE1 Bootstrap word 3 */

#define FEE2_MCR    (volatile short *)(ABase+0x820)  /* FEE2(48K) Module Confg.Reg.(FEE2MCR)(word)*/
#define FEE2_TST    (volatile short *)(ABase+0x822)  /* FEE2 Test Reg. (word) */
#define FEE2_BAH    (volatile short *)(ABase+0x824)  /* FEE2 Base Address High Reg. */
#define FEE2_BAL    (volatile short *)(ABase+0x826)  /* FEE2 Base Address High Reg. */
#define FEE2_CR     (volatile short *)(ABase+0x828)  /* FEE2 Control Reg. (word) */
#define FEE2_BS0    (volatile short *)(ABase+0x830)  /* FEE2 Bootstrap word 0 */
#define FEE2_BS1    (volatile short *)(ABase+0x832)  /* FEE2 Bootstrap word 1 */
#define FEE2_BS2    (volatile short *)(ABase+0x834)  /* FEE2 Bootstrap word 2 */
#define FEE2_BS3    (volatile short *)(ABase+0x836)  /* FEE2 Bootstrap word 3 */

/**************************** CONFIGURATION REGISTERS ***********************/
#define SIM_MCR     (volatile short *)(ABase+0xA00)  /* Module Configuration (word) */
#define SIM_SIMTR   (volatile short *)(ABase+0xA02)  /* Module Test Register (word) */

/******************************** CLOCK *************************************/
#define SIM_SYNCR   (volatile short *)(ABase+0xA04)  /* Clock Synthesizer Control (word)*/
#define SIM_RSR     (volatile char *)(ABase+0xA07) /* Reset Status Register (byte) */

/******************************** EBI ***************************************/
#define SIM_SIMTRE  (volatile short *)(ABase+0xA08)  /* Module Test E  (word) */
#define SIM_PORTA   (volatile char *)(ABase+0xA0A) /* Port A Data (byte) */
#define SIM_PORTB   (volatile char *)(ABase+0xA0B) /* Port B Data (byte) */
#define SIM_PORTG   (volatile char *)(ABase+0xA0C) /* Port G Data (byte) */
#define SIM_PORTH   (volatile char *)(ABase+0xA0D) /* Port H Data (byte) */
#define SIM_DDRG    (volatile char *)(ABase+0xA0E) /* Port G Data Direction (byte) */
#define SIM_DDRH    (volatile char *)(ABase+0xA0F) /* Port H Data Direction (byte) */

#define SIM_PORTE   (volatile char *)(ABase+0xA11) /* Port E Data (byte) */
#define SIM_PORTEq  (volatile char *)(ABase+0xA13) /* Port E Data(same as SIM_PORTE)(byte)*/

#define SIM_DDRAB   (volatile char *)(ABase+0xA14) /* Port A/B Data Direction (byte) */
#define SIM_DDRE    (volatile char *)(ABase+0xA15) /* Port E Data Direction (byte) */
#define SIM_PEPAR   (volatile char *)(ABase+0xA17) /* Port E Pin Assignment (byte) */
#define SIM_PORTF   (volatile char *)(ABase+0xA19) /* Port F Data (byte) */
#define SIM_PORTF2  (volatile char *)(ABase+0xA1B) /* Port F Data(same as SIM_PORTF)(byte)*/
#define SIM_DDRF    (volatile char *)(ABase+0xA1D) /* Port F Data Direction (byte) */
#define SIM_PFPAR   (volatile char *)(ABase+0xA1F) /* Port F Pin Assignment (byte) */

/******************************** SYSTEM PROTECTION *************************/
#define SIM_SYPCR   (volatile char *)(ABase+0xA21) /* System Protection Control (byte) */
#define SIM_PICR    (volatile short *)(ABase+0xA22)  /* Periodic shorterrupt Control (word)*/
#define SIM_PITR    (volatile short *)(ABase+0xA24)  /* Periodic Interrupt Timing (word) */
#define SIM_SWSR    (volatile char *)(ABase+0xA27) /* Software Service (byte) */

/**************************** Port F Edge Detect Register ********************/
#define SIM_PORTFE  (volatile char *)(ABase+0xA29) /* Port F Edge Detect Flags (byte)*/
#define SIM_PFIVR   (volatile char *)(ABase+0xA2B) /* Port F Edge Detect Vector(byte)*/
#define SIM_PFLVR   (volatile char *)(ABase+0xA2D) /* Port F Edge Detect Level (byte)*/

/******************************** TEST ***************************************/
#define SIM_TSTMSRA (volatile short *)(ABase+0xA30)  /* Test Module Master Shift A(word)*/
#define SIM_TSTMSRB (volatile short *)(ABase+0xA32)  /* Test Module Master Shift B(word)*/
#define SIM_TSTSC   (volatile short *)(ABase+0xA34)  /* TRest Module Shift Count (word) */
#define SIM_TSTRC   (volatile short *)(ABase+0xA36)  /* Test Module Repetition Counter(word)*/
#define SIM_CREG    (volatile short *)(ABase+0xA38)  /* Test Module Control (word) */
#define SIM_DREG    (volatile short *)(ABase+0xA3A)  /* Test Module Distributed Reg.(word)*/

/******************************** CHIP SELECT ********************************/
#define SIM_CSPDR   (volatile char *)(ABase+0xA41) /* Chip-Select Pin Data Register (byte)*/
                                           /* Port C Data (CSPDR)(byte) */
#define SIM_CSPAR0  (volatile short *)(ABase+0xA44)  /* Chip-select Pin Assignment (word)*/
#define SIM_CSPAR1  (volatile short *)(ABase+0xA46)  /* Chip-select Pin Assignment (word)*/
#define SIM_CSBARBT (volatile short *)(ABase+0xA48)  /* Chip-select Base Boot (word) */
#define SIM_CSORBT  (volatile short *)(ABase+0xA4A)  /* Chip-select Option Boot (word) */
#define SIM_CSBAR0  (volatile short *)(ABase+0xA4C)  /* Chip-select Base #0 (word) */
#define SIM_CSOP0   (volatile short *)(ABase+0xA4E)  /* Chip-select Option 0 (word) */

#define SIM_CSBAR1  (volatile short *)(ABase+0xA50)  /* Chip-select Base #1 (word)  */
#define SIM_CSOP1   (volatile short *)(ABase+0xA52)  /* Chip-select Option 1 (word) */
#define SIM_CSBAR2  (volatile short *)(ABase+0xA54)  /* Chip-select Base #2 (word)  */