📄 btc5w_boot.s
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;----------------------btc5w_boot------------------------------------------------
MODE_MASK EQU 0x1F ;Processor Mode Mask
UDF_MODE EQU 0x1B ;Undefine Mode(UDF)
ABT_MODE EQU 0x17 ;Abort Mode(ABT)
SUP_MODE EQU 0x13 ;Supervisor Mode (SVC)
IRQ_MODE EQU 0x12 ;Interrupt Mode (IRQ)
FIQ_MODE EQU 0x11 ;Fast Interrupt Mode (FIQ)
USR_MODE EQU 0x10 ;User Mode(USR)
;---------------------------------------------------------------------------------
;EBI BASE ADDRESS
;---------------------------------------------------------------------------------
EBI_BASE EQU 0xFFE00000 ;- External Bus Interface
EBI_CSR0 EQU 0xFFE00000
EBI_CSR1 EQU 0xFFE00004
EBI_CSR2 EQU 0xFFE00008
EBI_CSR3 EQU 0xFFE0000C
EBI_CSR4 EQU 0xFFE00010
EBI_CSR5 EQU 0xFFE00014
EBI_CSR6 EQU 0xFFE00018
EBI_CSR7 EQU 0xFFE0001C
EBI_MCR EQU 0xFFE00024
EBI_RCR EQU 0xFFE00020
;=========================================================================
EBI_CSR_0 EQU 0x01002529 ; 0x01002529, 片选使能，字节访问，2个tdf，基地址的有效位数为8位(31--24)，使能等待状态产生器，3个NWS， 16 bits。
EBI_CSR_1 EQU 0x02403121 ; 0x02403121, 片选使能，字节选择访问，基地址的有效位数为8位(31--24)，使能等待状态产生器，1个NWS，，16 bits。
EBI_CSR_2 EQU 0x0280252E ; 0x0280252E, 片选使能，字节访问, 2个tdf,基地址的有效位数为8位(31--24)，使能等待状态产生器，4个NSW， 8 bits。
EBI_CSR_3 EQU 0x03002102 ; 显示器片选
EBI_CSR_4 EQU 0x40000000 ; unused
EBI_CSR_5 EQU 0x50000000 ; unused
EBI_CSR_6 EQU 0x60000000 ; unused
EBI_CSR_7 EQU 0x70000000 ; unused
EBI_RCR_Remap EQU 0x00000001
;=========================================================================
SYSTEM_INIT_ADDR EQU 0x00000000
SYSTEM_BASE EQU 0x01000500
SYSTEM_END EQU 0x0100F500
RAM_BASE_BOOT EQU 0x00300000
FLASH_BASE EQU 0x01000000
EXT_SRAM_BASE EQU 0x02000000
;=========================================================================
APMC_BASE EQU 0xFFFF4000
APMC_CGMR EQU 0x20
APMC_SR EQU 0x30
APMC_MOSCS EQU 0x1
APMC_PLL_LOCK EQU 0x2
;=========================================================================
;=========================================================================
^ 0
AIC_SMR # 32*4 ;- Source Mode Register
AIC_SVR # 32*4 ;- Source Vector Register
AIC_IVR # 4 ;- IRQ Vector Register
AIC_FVR # 4 ;- FIQ Vector Register
AIC_ISR # 4 ;- Interrupt Status Register
AIC_IPR # 4 ;- Interrupt Pending Register
AIC_IMR # 4 ;- Interrupt Mask Register
AIC_CISR # 4 ;- Core Interrupt Status Register
# 4 ;- Reserved 0
# 4 ;- Reserved 1
AIC_IECR # 4 ;- Interrupt Enable Command Register
AIC_IDCR # 4 ;- Interrupt Disable Command Register
AIC_ICCR # 4 ;- Interrupt Clear Command Register
AIC_ISCR # 4 ;- Interrupt Set Command Register
AIC_EOICR # 4 ;- of Interrupt Command Register
AIC_SPU # 4 ;- Spurious Vector Register
AIC_BASE EQU 0xFFFFF000
;=========================================================================
AREA init, CODE, READONLY
;=========================================================================
ENTRY
B Boot_Handler
B Undefined_Handler
B SWI_Handler
B Prefetch_Handler
B Abort_Handler
NOP ; Reserved vector
B IRQ_Handler
B FIQ_Handler
;=========================================================================
; The Default Exception Handler Vector Entry Pointer Setup
;=========================================================================
Undefined_Handler
B Undefined_Handler
SWI_Handler
B SWI_Handler
Prefetch_Handler
B Prefetch_Handler
Abort_Handler
B Abort_Handler
SystemReserv
B SystemReserv
IRQ_Handler
B IRQ_Handler
FIQ_Handler
B FIQ_Handler
;=========================================================================
; The Default Exception Handler Vector Entry Pointer Setup
;=========================================================================
AREA Main, CODE, READONLY
Vector_Init_Block
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP
LDR PC,[PC,# - &F20]
LDR PC,[PC,# - &F20]
;=========================================================================
Reset_Addr DCD Reset_Handler
Undefined_Addr DCD Undefined_Handler
SWI_Addr DCD SWI_Handler
Prefetch_Addr DCD Prefetch_Handler
Abort_Addr DCD Abort_Handler
;=========================================================================
Boot_Handler
;=========================================================================
;- Speed up the System Frequency.配置外部时钟为系统时钟，无需等待
;=========================================================================
ldr r0, =0x00004001 ; M0SCBYP = 1,MOSCEN=0,MCKODS=0,PRES=0,MUL=0,CSS=1,OSCOUNT=0,PLLCOUNT=0
ldr r1, =APMC_BASE ; Get the APMC Base Address
str r0, [r1, #APMC_CGMR] ; Store the configuration of the Clock Generator
;=========================================================================
;setup the PLL
ldr r0,=0x03004201 ;M0SCBYP = 1，MOSCEN=0，MCKODS=0，PRES=0，MUL=2，CSS=1，OSCOUNT=0,PLLCOUNT=3.(预置的测试值)
str r0,[r1,#APMC_CGMR]
;=========================================================================
;读状态寄存器，等待PLL稳定
;-------------------------------------------------------------------------
mov r4,#APMC_PLL_LOCK
PLL_Loop
ldr r3,[r1,#APMC_SR]
and r3,r4,r3
cmp r3,#APMC_PLL_LOCK
bne PLL_Loop
;输出PLL倍频--------------------------------------------------------------
ldr r0,=0x03008201
str r0,[r1,#APMC_CGMR]
;- Load System EBI Base address and CSR0 Init Value
LDR r0, =EBI_CSR0
LDR r1, =EBI_CSR_0
STR r1,[r0]
LDR r0, =EBI_CSR1
LDR r1, =EBI_CSR_1
STR r1,[r0]
LDR r0, =EBI_CSR2
LDR r1, =EBI_CSR_2
STR r1,[r0]
LDR r0, =EBI_CSR3
LDR r1, =EBI_CSR_3
STR r1,[r0]
LDR r0, =EBI_CSR4
LDR r1, =EBI_CSR_4
STR r1,[r0]
LDR r0, =EBI_CSR5
LDR r1, =EBI_CSR_5
STR r1,[r0]
LDR r0, =EBI_CSR6
LDR r1, =EBI_CSR_6
STR r1,[r0]
LDR r0, =EBI_CSR7
LDR r1, =EBI_CSR_7
STR r1,[r0]
;=========================================================================
;copy vector_init_block to the ram that will be remap to 0x00000000
MOV R8, #RAM_BASE_BOOT ; @ of the hard vector in internal RAM 0x300000
ADD R9, PC,#-(8+.-Vector_Init_Block) ; @ where to read values (relative)
LDMIA R9!, {R0-R7} ; read 8 vectors
STMIA R8!, {R0-R7} ; store them
LDMIA R9!, {R0-R4} ; read 5 absolute handler addresses
STMIA R8!, {R0-R4} ; store them
;copy entry point to the place where after remap
LDR R8, =REMAP_End
MOV R9, #SYSTEM_INIT_ADDR
SUB R7, R8,R9
ADD R6, R7,#RAM_BASE_BOOT
ADD R9, PC,#-(8+.-REMAP_End)
LDMIA R9!, {R0-R3}
STMIA R6!, {R0-R3}
LDR R0, =EBI_RCR
LDR R1, =EBI_RCR_Remap
STR R1,[R0]
REMAP_End
NOP
NOP
NOP
B Reset_Handler+FLASH_BASE
;=========================================================================
Reset_Handler
NOP
NOP
NOP
MOV R0, #EXT_SRAM_BASE
LDR R1, =SYSTEM_BASE ; and RAM copy
LDR R3, =SYSTEM_END ; Zero init base => top of initialised data
Loop_Ram_Copy
CMP R1, R3 ; Copy init data
LDRCC R2, [R1], #4
STRCC R2, [R0], #4
BCC Loop_Ram_Copy
NOP
NOP
NOP
LDR PC,=EXT_SRAM_BASE
END
;=========================================================================
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