📄 os_cpu_a.s
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; Calls the IRQ dispatcher
; Checks if context switch necessary
; If not, restores context and returns from interrupt
; If switch required, branches without link to IRQContextSwap
; which performs context switch if interrupts not nested
; and returns from interrupt to new context
;
; Parameters: void
;
; Outputs: None
;
; Returns: void
;
; Notes:
; (1) here we use OSIntCtxSwFlag to indicate a request for int-level
; context switch
; (2) _IntCtxSw is used to perform a real switch operation
;
;*********************************************************************/
;----------------------------------------------------------------------
; modified by YJ
;----------------------------------------------------------------------
; added starts <<------------------------------------------------------
EXPORT OSTickISR
IMPORT OSIntEnter
IMPORT OSTimeTick
IMPORT CLEARBIT
IMPORT OSIntExit
IMPORT OSIntCtxSwFlag
LINK_SAVE DCD 0
PSR_SAVE DCD 0
OSTickISR
; STMFD sp!, {lr} ; push pc (lr is actually be pushed in place of PC)
; STMFD sp!, {r0-r12,lr} ; push lr & register file
; MRS r4, cpsr
; STMFD sp!, {r4} ; push current psr
; BL OSIntEnter
STMFD SP!,{R0-R3,R12,LR}
BL OSIntEnter ; Indicate beginning of ISR
; BL DmpStk
BL OSTimeTick
BL CLEARBIT
; BL Tmr_TickISR_Handler ; Handle interrupt (see BSP.C)
BL OSIntExit ; Indicate end of ISR
LDR R0,=OSIntCtxSwFlag ; See if we need to do a context switch
LDR R1,[R0]
CMP R1,#1
BEQ OS_IntCtxSw ; Yes, Switch to Higher Priority Task
LDMFD SP!,{R0-R3,R12,LR} ; No, Restore registers of interrupted task's stack
SUBS PC,LR,#4 ; Return from IRQ
; STMFD sp!, {r4}
;
; LDR r4, =LINK_SAVE
; STR lr, [r4] ; LINK_SAVE = lr_irq
; MRS lr, spsr
; STR lr, [r4, #4] ; PSR_SAVE = spsr_irq
; LDMFD sp!, {r4}
; ORR lr, lr, #0xc0 ; Mask irq for context switching before
; MSR cpsr_cxsf, lr ; returning back from irq mode.
; SUB sp, sp, #4 ; Space for PC
; STMFD sp!, {r0-r12, lr}
; LDR r4, =LINK_SAVE
; LDR lr, [r4, #0]
; SUB lr, lr, #4 ; lr = LINK_SAVE - 4,
; STR lr, [sp, #(14*4)] ; the return address for pc.
; LDR r4, [r4, #4] ; r4 = PSR_SAVE,
; STMFD sp!, {r4} ; CPSR of the task
; LDR r4, =OSTCBCur
; LDR r4, [r4]
; STR sp, [r4] ; OSTCBCur -> stkptr = sp
BL CLEARBIT
; BL DmpStk
BL OSTimeTick
; BL OSIntExit
; BL DmpStk
;LDR r4, =OSTCBHighRdy
; LDR r4, [r4]
; LDR sp, [r4]
; LDMFD sp!, {r4} ; pop new task cpsr
; MSR cpsr_cxsf, r4
; LDMFD sp!, {r0-r12,lr,pc} ; pop new task r0-r12,lr & pc
; SUBS PC,LR,#4 ; Return from IRQ
; --------------------------------------------------------->> added ends
;emoved starts <<-----------------------------------------------------
;SAVED_LR_SVC DCD 0x00000000 ; some variables for temparal use
;SAVED_LR_IRQ DCD 0x00000000
;SAVED_SPSR DCD 0x00000000
;INTPND DCD 0x03ff4004 ;IRQ controller
; EXPORT OSTickISR
; IMPORT OSIntEnter
; IMPORT OSTimeTick
; IMPORT timer_irq
; IMPORT OSIntExit
; IMPORT OSIntCtxSwFlag
;OSTickISR
; SUB lr, lr, #4
; STMFD sp!, {r0-r12, lr} ; push r0-r12 register file and lr( pc return address )
; MRS r4, spsr
; STMFD sp!, {r4} ; push current spsr_cxsf_irq ( =cpsr_svc )
; ; -- identify source of interrupt .........................
; LDR r0, INTPND
; LDR r0, [r0]
; TST r0, #0x0400
; BNE handler_event_timer
; LDMFD sp!, {r4} ; get cpsr_svc from stack
; MSR spsr_cxsf, r4 ; prepare spsr_cxsf to return svc mode
; LDMFD sp!, {r0-r12, pc}^ ; recover r0-r12 and pc from stack, cpsr also
;handler_event_timer
; BL OSIntEnter
; BL OSTimeTick
; BL timer_irq ; here do_IRQ is used to clear some virtual-hardware flags
; BL OSIntExit
; LDR r0, =OSIntCtxSwFlag ; check if OSIntCtxFlag is marked as true
; LDR r1, [r0]
; CMP r1, #1
; BEQ _IntCtxSw ; if OSIntCtxFlag = true, then jump to _IntCtxSw
;_IntCtxSw
; MOV r1, #0 ; clear OSIntCtxSwFlag = flase
; STR r1, [r0]
; LDMFD sp!, {r4} ; restore spsr_cxsf_irq
; MSR spsr_cxsf, r4
; str r4, SAVED_SPSR
; LDMFD sp!, {r0-r12, lr} ; recover the irq stack pointer
; STR lr, SAVED_LR_IRQ ; save lr_irq to SAVED_LR_IRQ
; MOV lr, #0x000000d3 ; change forcely cpsr to svc mode
; MSR cpsr_cxsf, lr
; STR lr, SAVED_LR_SVC ; save lr_svc to SAVED_LR_SVC
; LDR lr, SAVED_LR_IRQ ; get lr_irq value saved in SAVED_LR_IRQ
; STMFD sp!, {lr} ; push future task pc (lr_irq should be pushed in place of PC)
; LDR lr, SAVED_LR_SVC ; get lr_svc value saved in SAVED_LR_SVC
; STMFD sp!, {r0-r12,lr} ; push lr & r0-r12 register file
; ldr r4, SAVED_SPSR
; ; MRS r4, spsr
; STMFD sp!, {r4} ; push current psr
; ; MRS r4, spsr
; STMFD sp!, {r4} ; push spsr_cxsf
; B _OSCtxSw ; jump to _OSCtxSw
; --------------------------------------------------------->> removed ends
;/***********************************************************************
;
; Functions: ARMDisableInt
; ARMEnableInt
;
; Purpose:
; Disable and enable IRQ and FIQ preserving current CPU mode.
;
; Processing:
; Push the cpsr onto the stack
; Disable IRQ and FIQ interrupts
; Return
;
; Parameters: void
;
; Outputs: None
;
; Returns: void
;
; Notes:
; (1) Can be called from SVC mode to protect Critical Sections.
; (2) Do not use these calls at interrupt level.
; (3) Used in pairs within the same function level;
; (4) Will restore interrupt state when called; i.e., if interrupts
; are disabled when DisableInt is called, interrupts will still
; still be disabled when the matching EnableInt is called.
; (5) Uses the method described by Labrosse as "Method 2".
;
;*********************************************************************/
; EXPORT ARMDisableInt
;ARMDisableInt
; MRS r0, cpsr
; STMFD sp!, {r0} ; push current PSR
; ORR r0, r0, #0xC0
; MSR cpsr_c, r0 ; disable IRQ Int s
; MOV pc, lr
; EXPORT ARMEnableInt
;ARMEnableInt
; LDMFD sp!, {r0} ; pop current PSR
; MSR cpsr_c, r0 ; restore original cpsr
; MOV pc, lr
EXPORT OS_CPU_SR_Save
EXPORT OS_CPU_SR_Restore
; EXPORT ARMDisableInt
; EXPORT ARMEnableInt
OS_CPU_SR_Save
MRS R0,CPSR ; Set IRQ and FIQ bits in CPSR to disable all interrupts
ORR R1,R0,#0xC0
MSR CPSR_c,R1
MRS R1,CPSR ; Confirm that CPSR contains the proper interrupt disable flags
AND R1,R1,#0xC0
CMP R1,#0xC0
BNE OS_CPU_SR_Save ; Not properly disabled (try again)
MOV PC,LR ; Disabled, return the original CPSR contents in R0
;--------------------------------------------------------------------------------------
;ARMDisableInt
; mrs r12, SPSR ;get current CPU mode
; orr r12, r12, #I_BIT ;set the interrupt disable mode bit
; msr SPSR_c, r12
; bx lr
;--------------------------------------------------------------------------------------
OS_CPU_SR_Restore
MSR CPSR_c,R0
MOV PC,LR
;--------------------------------------------------------------------------------------
;ARMEnableInt
; mrs r12, SPSR ;move current processor status into reg 12
; bic r12, r12, #I_BIT ;clear the interrupt disable bit
; msr SPSR_c, r12
; bx lr
;--------------------------------------------------------------------------------------
;---------------------------------------------------------------------
; function : dump stack
; Added by YJ for debug
;---------------------------------------------------------------------
END
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