readme.txt

一个基于can_bus的虚拟程序

CAN Core Architecture

can_top.vhd                           <-- Top level sysnthesis module
     can_bsp.vhd                      <-- CAN bit stream Procesor
           can_acf.vhd                <-- Acceptance Code filter
           can_crc.vhd                <-- CRC Generator
           can_fifo.vhd               <-- CAN fifio :)
     can_btl.vhd                      <-- CAN Bit timing Logic
     can_registers.vhd                <-- Configuration Registers of CAN
            can_register.vhd          <-- Register with Activie High Write enable
            can_register_asyn.vhd     <-- Register with Asynchronous reset
            can_register_asyn_syn.vhd <-- Register with Asynchronous and Synchronous Resets

The verilog files are part of the test bench of the verilog CAN core and as such won't be of any
use but if you are interested in verifying this core you can re write these in VHDL in order to test
 the core. The core is un-tested and un-verrified at the moment.

All constructs in the core are synthesizable

ModelSim user can use the following command line for compilation

vcom -93 -explicit *.vhd

For more information on CAN you can got to http://www.can.bosch.com/