can_top.vhd

一个基于can_bus的虚拟程序

-- Output signals from can_btl module 
signal  clk_en        : std_logic;
signal  sample_point  : std_logic;
signal  sampled_bit   : std_logic;
signal  sampled_bit_q : std_logic;
signal  tx_point      : std_logic;
signal  hard_sync     : std_logic;
signal  resync        : std_logic;


-- output from can_bsp module 
signal  rx_idle           : std_logic;
signal  transmitting      : std_logic;
signal  last_bit_of_inter : std_logic;


begin

wb_ack_o <= wb_ack_o_reg;

-- Connecting can_registers module 
i_can_registers: can_registers
port map 
( 
   clk      => clk
  ,rst      => wb_rst_i
  ,cs       => cs
  ,we       => wb_we_i
  ,addr     => wb_adr_i
  ,data_in  => wb_dat_i
  ,data_out => data_out_regs

  -- Mode register 
  ,reset_mode             => reset_mode
  ,listen_only_mode       => listen_only_mode
  ,acceptance_filter_mode => acceptance_filter_mode
  ,sleep_mode             => sleep_mode

  -- Command register 
  ,clear_data_overrun => open
  ,release_buffer     => release_buffer
  ,abort_tx           => open
  ,tx_request         => tx_request
  ,self_rx_request    => open

  -- Bus Timing 0 register 
  ,baud_r_presc    => baud_r_presc
  ,sync_jump_width => sync_jump_width

  -- Bus Timing 1 register 
  ,time_segment1   => time_segment1
  ,time_segment2   => time_segment2
  ,triple_sampling => triple_sampling

  -- Clock Divider register 
  ,extended_mode => extended_mode
  ,rx_int_enable => rx_int_enable
  ,clock_off     => clock_off
  ,cd            => cd
  
  -- This section is for BASIC and EXTENDED mode 
  -- Acceptance code register 
  ,acceptance_code_0 => acceptance_code_0

  -- Acceptance mask register 
  ,acceptance_mask_0 => acceptance_mask_0
  -- End: This section is for BASIC and EXTENDED mode 
  
  -- This section is for EXTENDED mode 
  -- Acceptance code register 
  ,acceptance_code_1 => acceptance_code_1
  ,acceptance_code_2 => acceptance_code_2
  ,acceptance_code_3 => acceptance_code_3

  -- Acceptance mask register 
  ,acceptance_mask_1 => acceptance_mask_1
  ,acceptance_mask_2 => acceptance_mask_2
  ,acceptance_mask_3 => acceptance_mask_3
  -- End: This section is for EXTENDED mode 

  -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data 
  ,tx_data_0 => tx_data_0
  ,tx_data_1 => tx_data_1
  ,tx_data_2 => tx_data_2
  ,tx_data_3 => tx_data_3
  ,tx_data_4 => tx_data_4
  ,tx_data_5 => tx_data_5
  ,tx_data_6 => tx_data_6
  ,tx_data_7 => tx_data_7
  ,tx_data_8 => tx_data_8
  ,tx_data_9 => tx_data_9
  ,tx_data_10 => tx_data_10
  ,tx_data_11 => tx_data_11
  ,tx_data_12 => tx_data_12
  -- End: Tx data registers 

);





-- Connecting can_btl module 
i_can_btl: can_btl 
port map
( 
   clk => clk
  ,rst => wb_rst_i
  ,rx  => rx

  -- Mode register 
  ,reset_mode => reset_mode

  -- Bus Timing 0 register 
  ,baud_r_presc    => baud_r_presc
  ,sync_jump_width => sync_jump_width

  -- Bus Timing 1 register 
  ,time_segment1   => time_segment1
  ,time_segment2   => time_segment2
  ,triple_sampling => triple_sampling

  -- Output signals from this module 
  ,clk_en        => clk_en
  ,sample_point  => sample_point
  ,sampled_bit   => sampled_bit
  ,sampled_bit_q => sampled_bit_q
  ,tx_point      => tx_point
  ,hard_sync     => hard_sync
  ,resync        => resync

  
  -- output from can_bsp module 
  ,rx_idle           => rx_idle
  ,transmitting      => transmitting
  ,last_bit_of_inter => last_bit_of_inter
  
);



i_can_bsp: can_bsp 
port map
(
   clk => clk
  ,rst => wb_rst_i
  
  -- From btl module 
  ,sample_point  => sample_point
  ,sampled_bit   => sampled_bit
  ,sampled_bit_q => sampled_bit_q
  ,tx_point      => tx_point
  ,hard_sync     => hard_sync

  ,addr     => wb_adr_i
  ,data_out => data_out_fifo

  -- Mode register 
  ,reset_mode             => reset_mode
  ,acceptance_filter_mode => acceptance_filter_mode
  
  -- Command register 
  ,release_buffer => release_buffer
  ,tx_request     => tx_request

  -- Clock Divider register 
  ,extended_mode => extended_mode

  -- output from can_bsp module 
  ,rx_idle           => rx_idle
  ,transmitting      => transmitting
  ,last_bit_of_inter => last_bit_of_inter
  
  -- This section is for BASIC and EXTENDED mode 
  -- Acceptance code register 
  ,acceptance_code_0 => acceptance_code_0

  -- Acceptance mask register 
  ,acceptance_mask_0 => acceptance_mask_0
  -- End: This section is for BASIC and EXTENDED mode 
  
  -- This section is for EXTENDED mode 
  -- Acceptance code register 
  ,acceptance_code_1 => acceptance_code_1
  ,acceptance_code_2 => acceptance_code_2
  ,acceptance_code_3 => acceptance_code_3

  -- Acceptance mask register 
  ,acceptance_mask_1 => acceptance_mask_1
  ,acceptance_mask_2 => acceptance_mask_2
  ,acceptance_mask_3 => acceptance_mask_3
  -- End: This section is for EXTENDED mode 

  -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data 
  ,tx_data_0  => tx_data_0
  ,tx_data_1  => tx_data_1
  ,tx_data_2  => tx_data_2
  ,tx_data_3  => tx_data_3
  ,tx_data_4  => tx_data_4
  ,tx_data_5  => tx_data_5
  ,tx_data_6  => tx_data_6
  ,tx_data_7  => tx_data_7
  ,tx_data_8  => tx_data_8
  ,tx_data_9  => tx_data_9
  ,tx_data_10 => tx_data_10
  ,tx_data_11 => tx_data_11
  ,tx_data_12 => tx_data_12
  -- End: Tx data registers 
  
  -- Tx signal 
  ,tx     => tx
  ,tx_oen => tx_oen
);


-- Multiplexing wb_dat_o from registers and rx fifo
process(extended_mode,wb_adr_i,reset_mode)
begin
  if (extended_mode = '1' and reset_mode = '0'  and
     (((wb_adr_i >= conv_std_logic_vector(16,8)) and 
       (wb_adr_i <= conv_std_logic_vector(28,8)))
      or ( extended_mode = '0' and 
      ((wb_adr_i >= conv_std_logic_vector(20,8)) and 
       (wb_adr_i <= conv_std_logic_vector(29,8)))))) then
    data_out_fifo_selected <= '1';
  else
    data_out_fifo_selected <= '0';
end if;
end process;


wb_dat_o <= data_out_fifo when data_out_fifo_selected = '1' else data_out_regs;



-- Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk clock domain. 
process(clk)
begin
if(clk = '1' and clk'event) then
  if (cs_rst2 = '1') then
      cs_sync1 <= '0' after Tp;
      cs_sync2 <= '0' after Tp;
      cs_sync3 <= '0' after Tp;
  else
      cs_sync1 <= (wb_cyc_i and wb_stb_i) after Tp;
      cs_sync2 <=  cs_sync1 after Tp;
      cs_sync3 <=  cs_sync2 after Tp;
  end if;
end if;
end process;


cs <= cs_sync2 and (not cs_sync3);


process(wb_clk_i)
begin
if(wb_clk_i = '1' and wb_clk_i'event) then
  if (wb_ack_o_reg = '1') then
      cs_rst1 <= '0' after Tp;
      cs_rst2 <= '0' after Tp;
      cs_rst3 <= '0' after Tp;
  else
      cs_rst1 <= cs_sync2 after Tp;
      cs_rst2 <= cs_rst1  after Tp;
      cs_rst3 <= cs_rst2  after Tp;
  end if;
end if;
end process;


-- Generating acknowledge signal
process(wb_clk_i)
begin
if(wb_clk_i = '1' and wb_clk_i'event) then
  wb_ack_o_reg <= (cs_rst2 and (not cs_rst3)) after Tp;
end if;
end process;

end RTL;