can_top.vhd

一个基于can_bus的虚拟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

entity can_top is
port ( 
         wb_clk_i: in  std_logic ;
         wb_rst_i: in  std_logic ;
         wb_dat_i: in  std_logic_vector(7 downto 0);
         wb_dat_o: out std_logic_vector(7 downto 0);
         wb_cyc_i: in  std_logic ;
         wb_stb_i: in  std_logic ;
         wb_we_i : in  std_logic ;
         wb_adr_i: in  std_logic_vector(7 downto 0);
         wb_ack_o: out std_logic ;
         clk     : in  std_logic ;
         rx      : in  std_logic ;
         tx      : out std_logic ;
         tx_oen  : out std_logic);
end can_top;

architecture RTL of can_top is

component can_registers is
port (

         clk :    in std_logic;
         rst :    in std_logic;
         cs  :    in std_logic;
         we  :    in std_logic;
         addr:    in std_logic_vector(7 downto 0);
         data_in: in std_logic_vector(7 downto 0);
        
         data_out: out std_logic_vector(7 downto 0);

        

-- Mode register 
         reset_mode:             out std_logic;
         listen_only_mode:       out std_logic;
         acceptance_filter_mode: out std_logic;
         sleep_mode:             out std_logic;

-- Command register 
         clear_data_overrun: out std_logic;
         release_buffer:     out std_logic;
         abort_tx:           out std_logic;
         tx_request:         out std_logic;
         self_rx_request:    out std_logic;

-- Bus Timing 0 register 
         baud_r_presc:    out std_logic_vector(5 downto 0);
         sync_jump_width: out std_logic_vector(1 downto 0);


-- Bus Timing 1 register 
         time_segment1:   out std_logic_vector(3 downto 0);
         time_segment2:   out std_logic_vector(2 downto 0);
         triple_sampling: out std_logic;
        
-- Clock Divider register 
         extended_mode: out std_logic;
         rx_int_enable: out std_logic;
         clock_off:     out std_logic;
         cd:            out std_logic_vector(2 downto 0);
        

-- This section is for BASIC and EXTENDED mode 
-- Acceptance code register 
        acceptance_code_0: out std_logic_vector(7 downto 0);

-- Acceptance mask register 
        acceptance_mask_0: out std_logic_vector(7 downto 0);

-- End: This section is for BASIC and EXTENDED mode 


-- This section is for EXTENDED mode 
-- Acceptance code register 
       acceptance_code_1: out std_logic_vector(7 downto 0);
       acceptance_code_2: out std_logic_vector(7 downto 0);
       acceptance_code_3: out std_logic_vector(7 downto 0);

-- Acceptance mask register 
       acceptance_mask_1: out std_logic_vector(7 downto 0);
       acceptance_mask_2: out std_logic_vector(7 downto 0);
       acceptance_mask_3: out std_logic_vector(7 downto 0);

-- End: This section is for EXTENDED mode 

-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data 
       tx_data_0 : out std_logic_vector(7 downto 0) ;
       tx_data_1 : out std_logic_vector(7 downto 0) ;
       tx_data_2 : out std_logic_vector(7 downto 0) ;
       tx_data_3 : out std_logic_vector(7 downto 0) ;
       tx_data_4 : out std_logic_vector(7 downto 0) ;
       tx_data_5 : out std_logic_vector(7 downto 0) ;
       tx_data_6 : out std_logic_vector(7 downto 0) ;
       tx_data_7 : out std_logic_vector(7 downto 0) ;
       tx_data_8 : out std_logic_vector(7 downto 0) ;
       tx_data_9 : out std_logic_vector(7 downto 0) ;
       tx_data_10: out std_logic_vector(7 downto 0) ;
       tx_data_11: out std_logic_vector(7 downto 0) ;
       tx_data_12: out std_logic_vector(7 downto 0));
--End: Tx data registers 

end component;

component can_btl is
port (

       clk: in std_logic;
       rst: in std_logic;
       rx : in std_logic;

--   Mode register 
       reset_mode: in std_logic;

-- Bus Timing 0 register 
       baud_r_presc    : in std_logic_vector(5 downto 0);
       sync_jump_width : in std_logic_vector(1 downto 0);

-- Bus Timing 1 register 
       time_segment1   : in std_logic_vector(3 downto 0);
       time_segment2   : in std_logic_vector(2 downto 0);
       triple_sampling : in std_logic;

-- Output from can_bsp module 
       rx_idle           : in std_logic;
       transmitting      : in std_logic;
       last_bit_of_inter : in std_logic;

-- Output signals from this module 
       clk_en        :  out std_logic ;
       sample_point  :  out std_logic ;
       sampled_bit   :  out std_logic ;
       sampled_bit_q :  out std_logic ;
       tx_point      :  out std_logic ;
       hard_sync     :  out std_logic ;
       resync        :  out std_logic);  
end component;

component can_bsp is
 port (
        clk:                    in std_logic;
        rst:                    in std_logic;
        sample_point:           in std_logic;
        sampled_bit:            in std_logic;
        sampled_bit_q:          in std_logic;
        tx_point:               in std_logic;
        hard_sync:              in std_logic;
        addr:                   in std_logic_vector(7 downto 0);
        data_out:               out std_logic_vector(7 downto 0);


        reset_mode:             in std_logic;
        acceptance_filter_mode: in std_logic;
        extended_mode:          in std_logic;


        release_buffer:         in std_logic;
        tx_request:             in std_logic;

        rx_idle:                out std_logic;
        transmitting:           out std_logic;
        last_bit_of_inter:      out std_logic;



        acceptance_code_0:      in std_logic_vector(7 downto 0);
        acceptance_mask_0:      in std_logic_vector(7 downto 0);


        acceptance_code_1:      in std_logic_vector(7 downto 0) ;
        acceptance_code_2:      in std_logic_vector(7 downto 0);
        acceptance_code_3:      in std_logic_vector(7 downto 0);


        acceptance_mask_1:      in std_logic_vector(7 downto 0);
        acceptance_mask_2:      in std_logic_vector(7 downto 0);
        acceptance_mask_3:      in std_logic_vector(7 downto 0);

        tx_data_0:              in std_logic_vector(7 downto 0);
        tx_data_1:              in std_logic_vector(7 downto 0);
        tx_data_2:              in std_logic_vector(7 downto 0);
        tx_data_3:              in std_logic_vector(7 downto 0);
        tx_data_4:              in std_logic_vector(7 downto 0);
        tx_data_5:              in std_logic_vector(7 downto 0);
        tx_data_6:              in std_logic_vector(7 downto 0);
        tx_data_7:              in std_logic_vector(7 downto 0);
        tx_data_8:              in std_logic_vector(7 downto 0);
        tx_data_9:              in std_logic_vector(7 downto 0);
        tx_data_10:             in std_logic_vector(7 downto 0);
        tx_data_11:             in std_logic_vector(7 downto 0);
        tx_data_12:             in std_logic_vector(7 downto 0);


        tx:                     out std_logic ;
        tx_oen:                 out std_logic);

end component;

constant     Tp: time := 1 ns;

signal  wb_ack_o_reg: std_logic;
signal  data_out_fifo_selected: std_logic;

signal  cs_sync1: std_logic;
signal  cs_sync2: std_logic;
signal  cs_sync3: std_logic;

signal  cs_rst1: std_logic;
signal  cs_rst2: std_logic;
signal  cs_rst3: std_logic;

signal  data_out_fifo: std_logic_vector(7 downto 0);
signal  data_out_regs: std_logic_vector(7 downto 0);


-- Mode register 
signal  reset_mode             : std_logic;
signal  listen_only_mode       : std_logic;
signal  acceptance_filter_mode : std_logic;
signal  sleep_mode             : std_logic;

-- Command register 
signal  release_buffer         : std_logic;
signal  tx_request             : std_logic;

-- Bus Timing 0 register 
signal  baud_r_presc           : std_logic_vector(5 downto 0);
signal  sync_jump_width        : std_logic_vector(1 downto 0);

-- Bus Timing 1 register 
signal  time_segment1          : std_logic_vector(3 downto 0);
signal  time_segment2          : std_logic_vector(2 downto 0);
signal  triple_sampling        : std_logic;

-- Clock Divider register 
signal  extended_mode          : std_logic;
signal  rx_int_enable          : std_logic;
signal  clock_off              : std_logic;
signal  cd                     : std_logic_vector(2 downto 0);

-- This section is for BASIC and EXTENDED mode 
-- Acceptance code register 
signal  acceptance_code_0      : std_logic_vector(7 downto 0);

-- Acceptance mask register 
signal  acceptance_mask_0      : std_logic_vector(7 downto 0);
-- End: This section is for BASIC and EXTENDED mode


-- This section is for EXTENDED mode 
-- Acceptance code register 
signal  acceptance_code_1      : std_logic_vector(7 downto 0);
signal  acceptance_code_2      : std_logic_vector(7 downto 0);
signal  acceptance_code_3      : std_logic_vector(7 downto 0);

-- Acceptance mask register 
signal  acceptance_mask_1      : std_logic_vector(7 downto 0);
signal  acceptance_mask_2      : std_logic_vector(7 downto 0);
signal  acceptance_mask_3      : std_logic_vector(7 downto 0);
-- End: This section is for EXTENDED mode 

-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data 
signal  tx_data_0              : std_logic_vector(7 downto 0);
signal  tx_data_1              : std_logic_vector(7 downto 0);
signal  tx_data_2              : std_logic_vector(7 downto 0);
signal  tx_data_3              : std_logic_vector(7 downto 0);
signal  tx_data_4              : std_logic_vector(7 downto 0);
signal  tx_data_5              : std_logic_vector(7 downto 0);
signal  tx_data_6              : std_logic_vector(7 downto 0);
signal  tx_data_7              : std_logic_vector(7 downto 0);
signal  tx_data_8              : std_logic_vector(7 downto 0);
signal  tx_data_9              : std_logic_vector(7 downto 0);
signal  tx_data_10             : std_logic_vector(7 downto 0);
signal  tx_data_11             : std_logic_vector(7 downto 0);
signal  tx_data_12             : std_logic_vector(7 downto 0);
-- End: Tx data registers 

signal  cs                     : std_logic;