can_register_asyn.vhd

来自「一个基于can_bus的虚拟程序」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

entity can_register_asyn is
generic(
         WIDTH       : integer := 8 ;
         RESET_VALUE : integer := 0);
port        
(
      data_in  : in std_logic_vector(WIDTH-1 downto 0)   ;
      we       : in std_logic                            ;
      clk      : in std_logic                            ;
      rst      : in std_logic                            ;

      data_out :  out std_logic_vector(WIDTH-1 downto 0));
end can_register_asyn;

architecture RTL of can_register_asyn is

signal data_out_reg: std_logic_vector(WIDTH-1 downto 0);

begin

process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if(rst = '1') then
    data_out_reg<= conv_std_logic_vector(RESET_VALUE,WIDTH) after 1 ns;
  elsif (we = '1') then        -- write
    data_out_reg<= data_in after 1 ns;
  end if;
end if;
end process;

data_out <= data_out_reg;

end RTL;