📄 can_registers.vhd
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-- End Clock Divider register
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
ACCEPTANCE_CODE_REG0: can_register
generic map
( WIDTH => 8)
port map
( data_in =>data_in
,data_out =>acceptance_code_0_reg
,we =>we_acceptance_code_0
,clk =>clk
);
-- End: Acceptance code register
-- Acceptance mask register
ACCEPTANCE_MASK_REG0: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => acceptance_mask_0_reg
,we => we_acceptance_mask_0
,clk => clk
);
-- End: Acceptance mask register
-- End: This section is for BASIC and EXTENDED mode
-- Tx data 0 register.
TX_DATA_REG0: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_0_reg
,we => we_tx_data_0
,clk => clk
);
-- End: Tx data 0 register.
-- Tx data 1 register.
TX_DATA_REG1: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_1_reg
,we => we_tx_data_1
,clk => clk
);
-- END: Tx data 1 register.
-- Tx data 2 register.
TX_DATA_REG2: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_2_reg
,we => we_tx_data_2
,clk => clk
);
-- End: Tx data 2 register.
-- Tx data 3 register.
TX_DATA_REG3: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_3_reg
,we => we_tx_data_3
,clk => clk
);
-- End: Tx data 3 register.
-- Tx data 4 register.
TX_DATA_REG4: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_4_reg
,we => we_tx_data_4
,clk => clk
);
-- End: Tx data 4 register.
-- Tx data 5 register.
TX_DATA_REG5: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_5_reg
,we => we_tx_data_5
,clk => clk
);
-- End: Tx data 5 register.
-- Tx data 6 register.
TX_DATA_REG6: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_6_reg
,we => we_tx_data_6
,clk => clk
);
-- End: Tx data 6 register.
-- Tx data 7 register.
TX_DATA_REG7: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_7_reg
,we => we_tx_data_7
,clk => clk
);
-- End: Tx data 7 register.
-- Tx data 8 register. */
TX_DATA_REG8: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_8_reg
,we => we_tx_data_8
,clk => clk
);
-- End: Tx data 8 register.
-- Tx data 9 register.
TX_DATA_REG9: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_9_reg
,we => we_tx_data_9
,clk => clk
);
-- End: Tx data 9 register.
-- Tx data 10 register.
TX_DATA_REG10: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_10_reg
,we => we_tx_data_10
,clk => clk
);
-- End: Tx data 10 register.
-- Tx data 11 register.
TX_DATA_REG11: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_11_reg
,we => we_tx_data_11
,clk => clk
);
-- End: Tx data 11 register.
-- Tx data 12 register.
TX_DATA_REG12: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => tx_data_12_reg
,we => we_tx_data_12
,clk => clk
);
-- End: Tx data 12 register.
-- This section is for EXTENDED mode
-- Acceptance code register 1
ACCEPTANCE_CODE_REG1: can_register
generic map
( WIDTH =>8)
port map
( data_in => data_in
,data_out => acceptance_code_1_reg
,we => we_acceptance_code_1
,clk => clk
);
-- End: Acceptance code register
-- Acceptance code register 2
ACCEPTANCE_CODE_REG2: can_register
generic map
( WIDTH =>8)
port map
( data_in => data_in
,data_out => acceptance_code_2_reg
,we => we_acceptance_code_2
,clk => clk
);
-- End: Acceptance code register
-- Acceptance code register 3
ACCEPTANCE_CODE_REG3: can_register
generic map
( WIDTH =>8)
port map
( data_in => data_in
,data_out => acceptance_code_3_reg
,we => we_acceptance_code_3
,clk => clk
);
-- End: Acceptance code register
-- Acceptance mask register 1
ACCEPTANCE_MASK_REG1: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => acceptance_mask_1_reg
,we => we_acceptance_mask_1
,clk => clk
);
-- End: Acceptance code register
-- Acceptance mask register 2
ACCEPTANCE_MASK_REG2: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => acceptance_mask_2_reg
,we => we_acceptance_mask_2
,clk => clk
);
-- End: Acceptance code register
-- Acceptance mask register 3
ACCEPTANCE_MASK_REG3: can_register
generic map
( WIDTH => 8)
port map
( data_in => data_in
,data_out => acceptance_mask_3_reg
,we => we_acceptance_mask_3
,clk => clk
);
-- End: Acceptance code register
-- End: This section is for EXTENDED mode
-- Reading data from registers
process( addr,read,extended_mode_reg,mode,bus_timing_0,bus_timing_1,clock_divider,
acceptance_code_0_reg,acceptance_code_1_reg,acceptance_code_2_reg,acceptance_code_3_reg,
acceptance_mask_0_reg,acceptance_mask_1_reg,acceptance_mask_2_reg,acceptance_mask_3_reg,
reset_mode_reg,tx_data_0_reg,tx_data_1_reg,tx_data_2_reg,tx_data_3_reg,tx_data_4_reg,
tx_data_5_reg,tx_data_6_reg,tx_data_7_reg,tx_data_8_reg,tx_data_9_reg
)
begin
if(read = '1') then -- read
if (extended_mode_reg = '1') then -- EXTENDED mode (Different register map depends on mode)
case addr is
when X"00" => data_out <= mode;
when X"01" => data_out <= X"00";
when X"06" => data_out <= bus_timing_0;
when X"07" => data_out <= bus_timing_1;
when X"10" => data_out <= acceptance_code_0_reg;
when X"11" => data_out <= acceptance_code_1_reg;
when X"12" => data_out <= acceptance_code_2_reg;
when X"13" => data_out <= acceptance_code_3_reg;
when X"14" => data_out <= acceptance_mask_0_reg;
when X"15" => data_out <= acceptance_mask_1_reg;
when X"16" => data_out <= acceptance_mask_2_reg;
when X"17" => data_out <= acceptance_mask_3_reg;
when X"18" => data_out <= X"00";
when X"19" => data_out <= X"00";
when X"1A" => data_out <= X"00";
when X"1B" => data_out <= X"00";
when X"1C" => data_out <= X"00";
when X"1F" => data_out <= clock_divider(7 downto 5)&'0'&clock_divider(3 downto 0);
when others => data_out <= X"00";
end case;
else -- BASIC mode
case addr is
when X"00" => data_out <= mode;
when X"01" => data_out <= X"FF";
when X"04" => if reset_mode_reg = '1' then data_out <= acceptance_code_0_reg; else data_out <=X"FF"; end if;
when X"05" => if reset_mode_reg = '1' then data_out <= acceptance_mask_0_reg; else data_out <=X"FF"; end if;
when X"06" => if reset_mode_reg = '1' then data_out <= bus_timing_0; else data_out <=X"FF"; end if;
when X"07" => if reset_mode_reg = '1' then data_out <= bus_timing_1; else data_out <=X"FF"; end if;
when X"0A" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_0_reg; end if;
when X"0B" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_1_reg; end if;
when X"0C" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_2_reg; end if;
when X"0D" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_3_reg; end if;
when X"0E" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_4_reg; end if;
when X"0F" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_5_reg; end if;
when X"10" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_6_reg; end if;
when X"11" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_7_reg; end if;
when X"12" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_8_reg; end if;
when X"13" => if reset_mode_reg = '1' then data_out <= X"FF"; else data_out <=tx_data_9_reg; end if;
when X"1F" => data_out <= clock_divider(7 downto 5)&'0'&clock_divider(3 downto 0);
when others => data_out <= X"00";
end case;
end if;
else
data_out <= X"00";
end if;
end process;
end RTL;
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