can_bsp.vhd

一个基于can_bus的虚拟程序

process(clk)
begin
if(clk = '1' and clk'event) then
  tx_point_q <= tx_point after Tp;
end if;
end process;


-- Changing bit order from (7 downto 0) to (0 downto 7) 
i_ibo_tx_data_0 :  can_ibo port map  (di=>tx_data_0 , do=>r_tx_data_0 );
i_ibo_tx_data_1 :  can_ibo port map (di=>tx_data_1 , do=>r_tx_data_1 );
i_ibo_tx_data_2 :  can_ibo port map (di=>tx_data_2 , do=>r_tx_data_2 );
i_ibo_tx_data_3 :  can_ibo port map (di=>tx_data_3 , do=>r_tx_data_3 );
i_ibo_tx_data_4 :  can_ibo port map (di=>tx_data_4 , do=>r_tx_data_4 );
i_ibo_tx_data_5 :  can_ibo port map (di=>tx_data_5 , do=>r_tx_data_5 );
i_ibo_tx_data_6 :  can_ibo port map (di=>tx_data_6 , do=>r_tx_data_6 );
i_ibo_tx_data_7 :  can_ibo port map (di=>tx_data_7 , do=>r_tx_data_7 );
i_ibo_tx_data_8 :  can_ibo port map (di=>tx_data_8 , do=>r_tx_data_8 );
i_ibo_tx_data_9 :  can_ibo port map (di=>tx_data_9 , do=>r_tx_data_9 );
i_ibo_tx_data_10:  can_ibo port map (di=>tx_data_10, do=>r_tx_data_10);
i_ibo_tx_data_11:  can_ibo port map (di=>tx_data_11, do=>r_tx_data_11);
i_ibo_tx_data_12:  can_ibo port map (di=>tx_data_12, do=>r_tx_data_12);

-- Changing bit order from (14 downto 0) to (0 downto 14) 
di_sig <= calculated_crc(6 downto 0)&'0';
i_calculated_crc0: can_ibo port map (di => calculated_crc(14 downto 7)   , do => r_calculated_crc(7  downto 0));
i_calculated_crc1: can_ibo port map (di => di_sig, do => r_calculated_crc(15 downto 8));


basic_chain         <= r_tx_data_1(7 downto 4)&"00"&r_tx_data_1(3 downto 0)&r_tx_data_0(7 downto 0)&'0';
basic_chain_data    <= r_tx_data_9&r_tx_data_8&r_tx_data_7&r_tx_data_6&r_tx_data_5&r_tx_data_4&r_tx_data_3&r_tx_data_2;
extended_chain_std  <= r_tx_data_0(7 downto 4)&"00"&r_tx_data_0(1)&r_tx_data_2(2 downto 0)&r_tx_data_1(7 downto 0)&'0';
extended_chain_ext  <= r_tx_data_0(7 downto 4)&"00"&r_tx_data_0(1)&r_tx_data_4(4 downto 0)&r_tx_data_3(7 downto 0)&r_tx_data_2(7 downto 3)&'1'&'1'&r_tx_data_2(2 downto 0)&r_tx_data_1(7 downto 0)&'0';
extended_chain_data <= r_tx_data_12&r_tx_data_11&r_tx_data_10&r_tx_data_9&r_tx_data_8&r_tx_data_7&r_tx_data_6&r_tx_data_5;

process(extended_mode,rx_data,tx_pointer,extended_chain_data,rx_crc,r_calculated_crc,
        r_tx_data_0,extended_chain_ext,extended_chain_std,basic_chain_data,basic_chain,
        finish_msg)
begin
  if (extended_mode = '1') then
      if (rx_data = '1') then  -- data stage
        tx_bit <= extended_chain_data(conv_integer(tx_pointer));
      elsif (rx_crc = '1') then
        tx_bit <= r_calculated_crc(conv_integer(tx_pointer));
      elsif (finish_msg = '1') then
        tx_bit <= '1';
      else
          if (r_tx_data_0(0) = '1') then    -- Extended frame
            tx_bit <= extended_chain_ext(conv_integer(tx_pointer));
          else
            tx_bit <= extended_chain_std(conv_integer(tx_pointer));
          end if;
      end if;
  else  -- Basic mode
      if (rx_data = '1') then  -- data stage
        tx_bit <= basic_chain_data(conv_integer(tx_pointer));
      elsif (rx_crc = '1') then
        tx_bit <= r_calculated_crc(conv_integer(tx_pointer));
      elsif (finish_msg = '1') then
        tx_bit <= '1';
      else
        tx_bit <= basic_chain(conv_integer(tx_pointer));
      end if;
  end if;
end process;


rst_tx_pointer <= '1' when (bit_de_stuff_tx = '0' and tx_point = '1' and rx_data = '0' and extended_mode = '1' and (tx_pointer = conv_std_logic_vector(38,6))) or  -- arbitration + control for extended format
                           (bit_de_stuff_tx = '0' and tx_point = '1' and rx_data = '0' and extended_mode = '0' and (tx_pointer = conv_std_logic_vector(18,6))) or  -- arbitration + control for standard format
                           (bit_de_stuff_tx = '0' and tx_point = '1' and rx_data = '1' and extended_mode = '1' and (tx_pointer = conv_std_logic_vector((8 * conv_integer(tx_data_0(3 downto 0)) - 1),6))) or  -- data
                           (bit_de_stuff_tx = '0' and tx_point = '1' and rx_data = '1' and extended_mode = '0' and (tx_pointer = conv_std_logic_vector((8 * conv_integer(tx_data_1(3 downto 0)) - 1),6))) or  -- data
                           (                     tx_point = '1' and   rx_crc_lim = '1'                                            ) or  -- crc
                           (go_rx_idle     = '1'                                                                                  ) or  -- at the end
                           (reset_mode     = '1'                                                                                  ) or
                           (overload_frame = '1'                                                                                  ) or
                           (error_frame    = '1'                                                                                  ) 
                       else '0';

process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    tx_pointer <= "000000";
  elsif (rst_tx_pointer = '1') then
    tx_pointer <= "000000" after Tp; 
  elsif (go_early_tx = '1' or (tx_point = '1' and tx_state = '1' and bit_de_stuff_tx = '0')) then
    tx_pointer <= tx_pointer + 1 after Tp;
  end if;
end if;
end process;


tx_successful <= '1' when ( transmitter = '1' and go_rx_inter = '1' and error_frame_ended = '0' and overload_frame_ended = '0' and priority_lost = '0') 
                     else '0';


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    need_to_tx <= '0';
  elsif (tx_successful = '1' or node_bus_off = '1') then
    need_to_tx <= '0';
  elsif (tx_request = '1') then
    need_to_tx <= '1' after Tp;
  end if;
end if;
end process;



go_early_tx <= '1' when need_to_tx = '1' and tx_state = '0' and suspend = '0' and sample_point = '1' and sampled_bit = '0' and (rx_idle_reg = '1' or last_bit_of_inter_reg = '1') else '0';
go_tx       <= '1' when need_to_tx = '1' and tx_state = '0' and suspend = '0' and (go_early_tx = '1' or rx_idle_reg = '1') else '0';


-- Tx state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    tx_state <= '0';
  elsif (go_rx_inter = '1' or error_frame = '1' or priority_lost = '1') then
    tx_state <= '0' after Tp;
  elsif (go_tx = '1') then
    tx_state <= '1' after Tp;
  end if;
end if;
end process;



-- Node is a transmitter
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    transmitter <= '0';
  elsif (go_tx = '1') then
    transmitter <= '1' after Tp;
  elsif (go_rx_inter = '1') then
    transmitter <= '0' after Tp;
  end if;
end if;
end process;



-- Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
-- Node might be both transmitter or receiver (sending error or overload frame)
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    transmitting <= '0';
  elsif (go_error_frame = '1' or go_overload_frame = '1' or go_tx = '1') then
    transmitting <= '1' after Tp;
  elsif (reset_mode = '1' or go_rx_idle = '1' or (go_rx_id1 = '1' and tx_state = '0') or (priority_lost = '1' and tx_state = '1')) then
    transmitting <= '0' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    suspend <= '0';
  elsif (reset_mode = '1' or (sample_point = '1' and (susp_cnt = conv_std_logic_vector(7,3)))) then
    suspend <= '0' after Tp;
  elsif (go_rx_inter = '1' and transmitter = '1' and node_error_passive = '1') then
    suspend <= '1' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then 
    susp_cnt_en <= '0';
  elsif (reset_mode = '1' or (sample_point = '1' and (susp_cnt = conv_std_logic_vector(7,3)))) then
    susp_cnt_en <= '0' after Tp;
  elsif (suspend = '1' and sample_point = '1' and last_bit_of_inter_reg = '1') then
    susp_cnt_en <= '1';
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    susp_cnt <= "000";
  elsif (reset_mode = '1' or (sample_point = '1' and (susp_cnt = conv_std_logic_vector(7,3)))) then
    susp_cnt <= "000" after Tp;
  elsif (susp_cnt_en = '1' and sample_point = '1') then
    susp_cnt <= susp_cnt + 1 after Tp;
  end if;
end if;
end process;




process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    finish_msg <= '0';
  elsif (go_rx_idle = '1' or go_rx_id1 = '1' or error_frame = '1' or reset_mode = '1') then
    finish_msg <= '0' after Tp;
  elsif (go_rx_crc_lim = '1') then
    finish_msg <= '1' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    priority_lost <= '0';
  elsif (go_rx_idle = '1' or error_frame = '1' or reset_mode = '1') then
    priority_lost <= '0';
  elsif (tx_state = '1' and sample_point = '1' and tx_reg = '1' and arbitration_field = '1') then
    priority_lost <= (not sampled_bit);
  end if;
end if;
end process;



process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_err_cnt <= (others => '0');
  elsif (reset_mode = '1') then
    rx_err_cnt <= (others => '0');
  else
      if (transmitter = '0' and go_rx_ack_lim = '1' and err = '0' and (rx_err_cnt > conv_std_logic_vector(0,10))) then
          if (rx_err_cnt > conv_std_logic_vector(127,10)) then
            rx_err_cnt <= conv_std_logic_vector(127,10) after Tp;
          else
            rx_err_cnt <= rx_err_cnt - 1 after Tp;
          end if;
      elsif ((rx_err_cnt < conv_std_logic_vector(1023,10)) and transmitter = '0') then
          if (go_error_frame_q = '1' and rule5 = '0') then                                                 -- 1  (rule 5 is just the opposite then rule 1 exception
            rx_err_cnt <= rx_err_cnt + 1;
          elsif ( (error_frame = '1' and sample_point = '1' and sampled_bit = '0' and error_cnt1_07 = '1' and rx_err_cnt_blocked = '0'     ) or   -- 2
                    (go_error_frame_q = '1' and rule5 = '1'                                                                                ) or   -- 5
                    (error_frame = '1' and sample_point = '1' and sampled_bit = '0' and (delayed_dominant_cnt = conv_std_logic_vector(7,3)))      -- 6
                 ) then
            rx_err_cnt <= rx_err_cnt + 4 after Tp ;
          end if;
      end if;
  end if; 
end if;
end process;

process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    tx_err_cnt <= (others => '0');
  elsif (reset_mode = '1' or node_bus_off = '1') then
    tx_err_cnt <= (others => '0');
  else
      if ((tx_err_cnt > conv_std_logic_vector(0,10)) and tx_successful = '1') then
        tx_err_cnt <= tx_err_cnt - 1;
      elsif ((tx_err_cnt < conv_std_logic_vector(1023,10)) and transmitter = '1') then
          if ( (sample_point = '1' and sampled_bit = '0' and (delayed_dominant_cnt = conv_std_logic_vector(7,3))   ) or  -- 6
               (error_flag_over = '1' and error_flag_over_blocked = '0' and rule5 = '1'                            ) or  -- 4  (rule 5 is the same as rule 4)
               (error_flag_over = '1' and error_flag_over_blocked = '0' and rule3_exc1_2 = '0' and rule3_exc2 = '0')     -- 3
             ) then
            tx_err_cnt <= tx_err_cnt + 4 after Tp;
          end if;
      end if;
  end if;
end if;
end process;



process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_err_cnt_blocked <= '0';
  elsif (reset_mode = '1' or error_frame_ended = '1') then
    rx_err_cnt_blocked <= '0' after Tp;
  elsif (sample_point = '1' and error_cnt1_07 = '1') then
    rx_err_cnt_blocked <= '1' after Tp;
  end if;
end if;
end process;



process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    node_error_passive <= '0';
  elsif (reset_mode = '1' or node_bus_off = '1' or ((rx_err_cnt < conv_std_logic_vector(128,10)) and (tx_err_cnt < conv_std_logic_vector(128,10)) and error_frame_ended = '1')) then
    node_error_passive <= '0' after Tp;
  elsif (((rx_err_cnt >= conv_std_logic_vector(128,10)) or (tx_err_cnt >= conv_std_logic_vector(128,10))) and error_frame_ended = '1') then
    node_error_passive <= '1' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    node_bus_off <= '0';
  elsif (reset_mode = '1' or ((rx_err_cnt = conv_std_logic_vector(0,10)) and (tx_err_cnt = conv_std_logic_vector(0,10)) and recessive_cnt_ok = '1')) then
    node_bus_off <= '0' after Tp;
  elsif (tx_err_cnt >= conv_std_logic_vector(256,10)) then
    node_bus_off <= '1' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    recessive_cnt <= "00000000000";
  elsif (sample_point = '1') then
      if (node_bus_off = '1' and sampled_bit = '1') then
        recessive_cnt <= recessive_cnt + 1 after Tp;
      else
        recessive_cnt <= "00000000000" after Tp;
      end if;
  end if;
end if;
end process;

recessive_cnt_ok <= '1' when (recessive_cnt = conv_std_logic_vector(128*11,11)) else '0';

tx_oen <= node_bus_off;

end RTL;