can_bsp.vhd

一个基于can_bus的虚拟程序

);




header_len(2 downto 0) <= "101" when (extended_mode = '1' and ide = '1') else
                          "011" when (extended_mode = '1' and ide = '0') else
                          "010";

storing_header <= '1' when (header_cnt < header_len) else '0';

limited_data_len_minus1(3 downto 0) <= X"F"           when (remote_rq = '1')                            else
                                       data_len - 1 when (remote_rq = '0' and data_len_less_08 = '1') else
                                       X"7";   -- - 1 because counter counts from 0

reset_wr_fifo <= '1' when ((data_cnt = (limited_data_len_minus1 + header_len)) or reset_mode = '1')
                    else '0';

err <= (form_err or stuff_err or bit_err or ack_err or form_err_latched or stuff_err_latched or bit_err_latched or ack_err_latched or crc_err);



-- Write enable signal for 64-byte rx fifo
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    wr_fifo <= '0';
  elsif (reset_wr_fifo = '1') then
    wr_fifo <= '0' after Tp;
--  elsif (go_rx_inter = '1' and id_ok = '1' and error_frame_ended = '0') then
-- FIX ME !!! Look following line
  elsif (go_rx_inter = '1' and id_ok = '1' and error_frame_ended = '0' and tx_state = '1') then
-- FIX ME !!! This line is the correct one. The above line is for easier debugging only.
    wr_fifo <= '1' after Tp;
  end if;
end if;
end process;


-- Header counter. Header length depends on the mode of operation and frame format.
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    header_cnt <= "000";
  elsif (reset_wr_fifo = '1') then
    header_cnt <= "000" after Tp;
  elsif (wr_fifo = '1' and storing_header = '1') then
    header_cnt <= header_cnt + 1 after Tp;
  end if;
end if;
end process;


-- Data counter. Length of the data is limited to 8 bytes.
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    data_cnt <= "0000";
  elsif (reset_wr_fifo = '1') then
    data_cnt <= "0000";
  elsif (wr_fifo = '1') then
    data_cnt <= data_cnt + 1 after Tp;
  end if;
end if;
end process;


-- Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
process(extended_mode,ide,data_cnt,header_cnt,header_len, 
          storing_header,id,rtr1,rtr2,data_len,
          tmp_fifo(0),tmp_fifo(2),tmp_fifo(4),tmp_fifo(6), 
          tmp_fifo(1),tmp_fifo(3),tmp_fifo(5),tmp_fifo(7) )
begin
  if (storing_header = '1') then
     if (extended_mode = '1') then      -- extended mode
         if (ide = '1') then            -- extended format
            case header_cnt is -- synthesis parallel_case 
                when "000"  =>  data_for_fifo <= '1'&rtr2&"00"&data_len;
                when "001"  =>  data_for_fifo <= id(28 downto 21);
                when "010"  =>  data_for_fifo <= id(20 downto 13);
                when "011"  =>  data_for_fifo <= id(12 downto  5);
                when "100"  =>  data_for_fifo <= id(4 downto 0)&"000";
                when others =>  data_for_fifo <= X"00";
              end case;
         else                  -- standard format
            case header_cnt is -- synthesis parallel_case 
                when "000"  => data_for_fifo <= '0'&rtr1&"00"&data_len;
                when "001"  => data_for_fifo <= id(10 downto 3);
                when "010"  => data_for_fifo <= id(2 downto 0)&"00000";
                when others => data_for_fifo <= X"00";
            end case;
         end if;
     else                    -- normal mode
        case header_cnt is -- synthesis parallel_case 
            when "000"  => data_for_fifo <= id(10 downto 3);
            when "001"  => data_for_fifo <= id(2 downto 0)&rtr1&data_len;
            when others => data_for_fifo <= X"00";
        end case;
     end if;
  else
    data_for_fifo <= tmp_fifo(conv_integer(data_cnt-header_len));
  end if;
end process;





-- Instantiation of the RX fifo module
i_can_fifo: can_fifo port map  
( 
  clk             => clk
  ,rst            => rst

  ,wr             => wr_fifo

  ,data_in        => data_for_fifo
  ,addr           => addr
  ,data_out       => data_out

  ,reset_mode     => reset_mode
  ,release_buffer => release_buffer
  ,extended_mode  => extended_mode
 
);


-- Transmitting error frame.
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    error_frame <= '0';
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_overload_frame = '1') then
    error_frame <= '0' after Tp;
  elsif (go_error_frame = '1') then
    error_frame <= '1' after Tp;
  end if;
end if;
end process;


process(clk)
begin
if(clk = '1' and clk'event) then
  if (sample_point = '1') then
    error_frame_q <= error_frame after Tp;
  end if;
end if;
end process;


process(clk)
begin
if(clk = '1' and clk'event) then
    go_error_frame_q <= go_error_frame after Tp;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    error_cnt1 <= "000";
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_error_frame = '1' or go_overload_frame = '1') then
    error_cnt1 <= "000" after Tp;
  elsif (error_frame = '1' and tx_point = '1' and error_cnt1_07 = '1') then
    error_cnt1 <= error_cnt1 + 1 after Tp;
  end if;
end if;
end process;



error_flag_over <= '1' when ( (node_error_passive = '0' and sample_point = '1' and error_cnt1_07 = '1' ) or
                     (node_error_passive = '1' and sample_point = '1' and sample_point = '1' and passive_cnt_05 = '1' and enable_error_cnt2 = '0')
                    ) else '0';


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    error_flag_over_blocked <= '0';
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_error_frame = '1' or go_overload_frame = '1') then
    error_flag_over_blocked <= '0' after Tp;
  elsif (error_flag_over = '1') then
    error_flag_over_blocked <= '1' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    enable_error_cnt2 <= '0';
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_error_frame = '1' or go_overload_frame = '1') then
    enable_error_cnt2 <= '0' after Tp;
  elsif (error_frame = '1' and (error_flag_over = '1' and sampled_bit = '1')) then
    enable_error_cnt2 <= '1' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    error_cnt2 <= "000";
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_error_frame = '1' or go_overload_frame = '1') then
    error_cnt2 <= "000" after Tp;
  elsif (enable_error_cnt2 = '1' and tx_point = '1') then
    error_cnt2 <= error_cnt2 + 1 after Tp;
  end if;
end if;
end process;



process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    delayed_dominant_cnt <= "000";
  elsif (reset_mode = '1' or enable_error_cnt2 = '1' or go_error_frame = '1' or enable_overload_cnt2 = '1' or go_overload_frame = '1') then
    delayed_dominant_cnt <= "000" after Tp;
  elsif (sample_point = '1' and sampled_bit = '0' and (error_cnt1_07 = '1' or overload_cnt1_07 = '1')) then
    delayed_dominant_cnt <= delayed_dominant_cnt + 1 after Tp;
  end if;
end if;
end process;

-- passive_cnt
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    passive_cnt <= "000";
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_error_frame = '1' or go_overload_frame = '1') then
    passive_cnt <= "000" after Tp;
  elsif (sample_point = '1' and passive_cnt_less_05 = '1') then
      if (error_frame_q = '1' and enable_error_cnt2 = '0' and (sampled_bit = sampled_bit_q)) then
        passive_cnt <= passive_cnt + 1 after Tp;
      else
        passive_cnt <= "000" after Tp;
      end if;
  end if;
end if;
end process;



-- Transmitting overload frame.
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    overload_frame <= '0';
  elsif (reset_mode = '1' or overload_frame_ended = '1' or go_error_frame = '1') then
    overload_frame <= '0' after Tp;
  elsif (go_overload_frame = '1') then
    overload_frame <= '1' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    overload_cnt1 <= "000";
  elsif (reset_mode = '1' or overload_frame_ended = '1' or go_error_frame = '1' or go_overload_frame = '1') then
    overload_cnt1 <= "000" after Tp;
  elsif (overload_frame = '1' and tx_point = '1' and overload_cnt1_less_07 = '1') then
    overload_cnt1 <= overload_cnt1 + 1;
  end if;
end if;
end process;


overload_flag_over <= sample_point and overload_cnt1_07 and (not enable_overload_cnt2);


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    enable_overload_cnt2 <= '0';
  elsif (reset_mode = '1' or overload_frame_ended = '1' or go_error_frame = '1' or go_overload_frame = '1') then
    enable_overload_cnt2 <= '0' after Tp;
  elsif (overload_frame = '1' and (overload_flag_over = '1' and sampled_bit = '1')) then
    enable_overload_cnt2 <= '1' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    overload_cnt2 <= "000";
  elsif (reset_mode = '1' or overload_frame_ended = '1'  or go_error_frame = '1' or go_overload_frame = '1') then
    overload_cnt2 <= "000" after Tp;
  elsif (enable_overload_cnt2 = '1' and tx_point = '1') then
    overload_cnt2 <= overload_cnt2 + 1 after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    overload_frame_blocked <= '0';
  elsif (reset_mode = '1' or go_error_frame = '1' or go_rx_id1 = '1') then
    overload_frame_blocked <= '0' after Tp;
  elsif (go_overload_frame = '1' and overload_frame = '1') then   -- This is a second sequential overload
    overload_frame_blocked <= '1' after Tp;
  end if;
end if;
end process;


send_ack <= (not tx_state) and rx_ack and (not err);


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    tx_reg <= '1';
  elsif (reset_mode = '1') then                                               -- Reset
    tx_reg <= '1' after Tp;
  elsif (tx_point = '1') then
      if (tx_state = '1') then                                                -- Transmitting message
        tx_reg <= ((not bit_de_stuff_tx) and tx_bit) or (bit_de_stuff_tx and (not tx_q)) after Tp;
      elsif (send_ack = '1') then                                                   -- Acknowledge
        tx_reg <= '0' after Tp;
      elsif (overload_frame = '1') then                                       -- Transmitting overload frame
          if (overload_cnt1_less_06 = '1') then
            tx_reg <= '0' after Tp;
          else
            tx_reg <= '1' after Tp;
          end if;
      elsif (error_frame = '1') then                                          -- Transmitting error frame
          if (error_cnt1_less_06 = '1') then
             if (node_error_passive = '1') then
                tx_reg <= '1' after Tp;
             else
                tx_reg <= '0' after Tp;
             end if;
          else
            tx_reg <= '1' after Tp;
          end if;
      else
        tx_reg <= '1' after Tp;
      end if;
  end if; 
end if;
end process;


process(clk)
begin
if(clk = '1' and clk'event) then
  if (tx_point = '1') then
    tx_q <= tx_reg after Tp; 
  end if;
end if;
end process;


-- Delayed tx point