can_bsp.vhd

一个基于can_bus的虚拟程序

  if (rst = '1') then
    write_data_to_tmp_fifo <= '0';
  elsif (sample_point = '1' and rx_data = '1' and bit_de_stuff = '0' and bit_cnt(2) = '1' and bit_cnt(1) = '1' and bit_cnt(0) = '1') then
    write_data_to_tmp_fifo <= '1' after Tp;
  else
    write_data_to_tmp_fifo <= '0' after Tp;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    byte_cnt <= "000";
  elsif (write_data_to_tmp_fifo = '1') then
    byte_cnt <= byte_cnt + 1 after Tp;
  elsif (sample_point = '1' and go_rx_crc_lim = '1') then
    byte_cnt <= "000" after Tp;
  end if;
end if;
end process;

process(clk)
begin
if(clk = '1' and clk'event) then
  if (write_data_to_tmp_fifo = '1') then
    tmp_fifo(conv_integer(byte_cnt)) <= tmp_data after Tp;
  end if;
end if;
end process;



-- CRC
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    crc_in <= "000000000000000";
  elsif (sample_point = '1' and rx_crc = '1' and bit_de_stuff = '0' ) then
    crc_in <=  crc_in(13 downto 0)&sampled_bit;
  end if;
end if;
end process;


-- bit_cnt
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    bit_cnt <= "000000";
  elsif (go_rx_id1 = '1' or go_rx_id2 = '1' or go_rx_dlc = '1' or go_rx_data = '1'  or go_rx_crc = '1' or 
           go_rx_ack = '1' or go_rx_eof = '1' or go_rx_inter = '1' or go_error_frame = '1' or go_overload_frame = '1') then
    bit_cnt <= "000000" after Tp;
  elsif (sample_point = '1' and bit_de_stuff = '0') then
    bit_cnt <= bit_cnt + 1 after Tp;
  end if;
end if;
end process;


-- eof_cnt
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    eof_cnt <= "000";
  elsif (sample_point = '1') then
      if (go_rx_inter = '1' or go_error_frame = '1' or go_overload_frame = '1') then
        eof_cnt <= "000" after Tp;
      elsif (rx_eof = '1') then
        eof_cnt <= eof_cnt + 1 after Tp;
      end if;
  end if;
end if;
end process;


-- Enabling bit de-stuffing
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    bit_stuff_cnt_en <= '0';
  elsif (bit_de_stuff_set = '1') then
    bit_stuff_cnt_en <= '1' after Tp;
  elsif (bit_de_stuff_reset = '1') then
    bit_stuff_cnt_en <= '0';
  end if;
end if;
end process;


-- bit_stuff_cnt
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    bit_stuff_cnt <= "111";
  elsif (bit_de_stuff_reset = '1') then
    bit_stuff_cnt <= "111" after Tp;
  elsif (sample_point = '1' and bit_stuff_cnt_en = '1') then
      if (bit_stuff_cnt = "101") then
        bit_stuff_cnt <= "111" after Tp;
      elsif (sampled_bit = sampled_bit_q) then
        bit_stuff_cnt <= bit_stuff_cnt + 1 after Tp;
      else
        bit_stuff_cnt <= "111" after Tp;
      end if;
  end if;
end if;
end process;


-- bit_stuff_cnt_tx
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    bit_stuff_cnt_tx <= "111";
  elsif (bit_de_stuff_reset = '1') then
    bit_stuff_cnt_tx <= "111" after Tp;
  elsif (tx_point_q = '1' and bit_stuff_cnt_en = '1') then
      if (bit_stuff_cnt_tx = "101") then
        bit_stuff_cnt_tx <= "111" after Tp;
      elsif (tx_reg = tx_q) then
        bit_stuff_cnt_tx <= bit_stuff_cnt_tx + 1 after Tp;
      else
        bit_stuff_cnt_tx <= "111";
      end if;
  end if;
end if;
end process;


bit_de_stuff    <= '1' when bit_stuff_cnt = "101" else '0';
bit_de_stuff_tx <= '1' when bit_stuff_cnt_tx = "101" else '0';



-- stuff_err
stuff_err <=  '1' when (sample_point = '1' and bit_stuff_cnt_en = '1'  and bit_de_stuff = '1' and (sampled_bit = sampled_bit_q)) else '0';



-- Generating delayed reset_mode signal
process(clk)
begin
if(clk = '1' and clk'event) then
  reset_mode_q <= reset_mode after Tp;
end if;
end process;



process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    crc_enable <= '0';
  elsif (go_crc_enable = '1') then
    crc_enable <= '1' after Tp;
  elsif (reset_mode = '1' or rst_crc_enable = '1') then
    crc_enable <= '0' after Tp;
  end if;
end if;
end process;


-- CRC error generation
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    crc_err <= '0';
  elsif (go_rx_ack = '1') then
   if (crc_in /= calculated_crc) then
    crc_err <= '1' after Tp;
   else
    crc_err <= '0' after Tp;
   end if;
  elsif (reset_mode = '1' or error_frame_ended = '1') then
    crc_err <= '0' after Tp;
  end if;
end if;
end process;

-- Conditions for form error
form_err <= (sample_point and ( ( (not bit_de_stuff) and rx_ide    and   sampled_bit and (not rtr1)        ) or
                                (                  rx_crc_lim and (not sampled_bit)                        ) or
                                (                  rx_ack_lim and (not sampled_bit)                        ) or
                                (eof_cnt_less_06   and rx_eof     and (not sampled_bit) and (not tx_state) ) or
                                (                    rx_eof     and (not sampled_bit) and   tx_state       )  ));

process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    ack_err_latched <= '0';
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_overload_frame = '1') then
    ack_err_latched <= '0' after Tp;
  elsif (ack_err = '1') then
    ack_err_latched <= '1' after Tp;
  end if;
end if;
end process;

process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    bit_err_latched <= '0';
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_overload_frame = '1') then
    bit_err_latched <= '0' after Tp;
  elsif (bit_err = '1') then
    bit_err_latched <= '1' after Tp;
  end if;
end if;
end process;



-- Rule 5 (Fault confinement).
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rule5 <= '0';
  elsif (reset_mode = '1' or error_flag_over = '1') then
    rule5 <= '0' after Tp;
  elsif ( node_error_passive = '0' and bit_err = '1' and bit_err_latched = '0' and  ((error_frame = '1' and error_cnt1_less_than_07 = '1') or 
                                                                    (overload_frame = '1' and overload_cnt1_less_07 = '1'))
         ) then
    rule5 <= '1' after Tp;
  end if;
end if;
end process;


-- Rule 3 exception 1 - first part (Fault confinement).
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rule3_exc1_1 <= '0';
  elsif (reset_mode = '1' or error_flag_over = '1' or rule3_exc1_2 = '1') then
    rule3_exc1_1 <= '0' after Tp;
  elsif (transmitter = '1' and node_error_passive = '1' and ack_err = '1') then
    rule3_exc1_1 <= '1' after Tp;
  end if;
end if;
end process;


-- Rule 3 exception 1 - second part (Fault confinement).
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rule3_exc1_2 <= '0';
  elsif (reset_mode = '1' or error_flag_over = '1') then
    rule3_exc1_2 <= '0' after Tp;
  elsif (rule3_exc1_1 = '1') then
    rule3_exc1_2 <=  '1' after Tp;
  elsif ( error_cnt1_less_than_07 = '1' and sample_point = '1' and sampled_bit = '0') then
    rule3_exc1_2 <= '0' after Tp;
  end if;
end if;
end process;


-- Rule 3 exception 2 (Fault confinement).
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rule3_exc2 <= '0';
  elsif (reset_mode = '1' or error_flag_over = '1') then
    rule3_exc2 <= '0' after Tp;
  elsif (transmitter = '1' and stuff_err = '1' and arbitration_field = '1' and sample_point = '1' and tx_reg = '1' and sampled_bit = '0') then
    rule3_exc2 <= '1' after Tp;
  end if;
end if;
end process;



process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    stuff_err_latched <= '0';
  elsif (reset_mode = '1' or  error_frame_ended = '1' or go_overload_frame = '1') then
    stuff_err_latched <= '0' after Tp;
  elsif (stuff_err = '1') then 
    stuff_err_latched <= '1' after Tp;
  end if;
end if;
end process;



process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    form_err_latched <= '0';
  elsif (reset_mode = '1' or error_frame_ended = '1' or go_overload_frame = '1') then
    form_err_latched <= '0' after Tp;
  elsif (form_err = '1') then
    form_err_latched <= '1' after Tp;
  end if;
end if;
end process;

enable_sig <= (crc_enable  and sample_point  and ( not bit_de_stuff));
initialize_sig <= (rx_eof  or go_error_frame  or go_overload_frame );

-- Instantiation of the RX CRC module
i_can_crc_rx: can_crc port map    
(
   clk        => clk
  ,data       => sampled_bit
  ,enable     => enable_sig
  ,initialize => initialize_sig
  ,crc        => calculated_crc
);




no_byte0 <= (rtr1 or data_len_less_01);
no_byte1 <= (rtr1 or data_len_less_02);

i_can_acf: can_acf port map  
(
   clk               => clk
  ,rst               => rst
  
  ,id                => id

  -- Mode register 
  ,reset_mode        => reset_mode
  ,acceptance_filter_mode => acceptance_filter_mode

  -- Clock Divider register
  ,extended_mode     => extended_mode
  
  -- This section is for BASIC and EXTENDED mode 
  -- Acceptance code register 
  ,acceptance_code_0 => acceptance_code_0

  -- Acceptance mask register 
  ,acceptance_mask_0 => acceptance_mask_0
  -- End: This section is for BASIC and EXTENDED mode 
  
  -- This section is for EXTENDED mode 
  -- Acceptance code register 
  ,acceptance_code_1 => acceptance_code_1
  ,acceptance_code_2 => acceptance_code_2
  ,acceptance_code_3 => acceptance_code_3

  -- Acceptance mask register 
  ,acceptance_mask_1 => acceptance_mask_1
  ,acceptance_mask_2 => acceptance_mask_2
  ,acceptance_mask_3 => acceptance_mask_3
  -- End: This section is for EXTENDED mode 

  ,go_rx_crc_lim     => go_rx_crc_lim
  ,go_rx_inter       => go_rx_inter
  ,go_error_frame    => go_error_frame
  
  ,data0             => tmp_fifo(0)
  ,data1             => tmp_fifo(1)
  ,rtr1              => rtr1
  ,rtr2              => rtr2
  ,ide               => ide
  ,no_byte0          => no_byte0
  ,no_byte1          => no_byte1

  ,id_ok             => id_ok