can_bsp.vhd

一个基于can_bus的虚拟程序

last_bit_of_inter <= last_bit_of_inter_reg;
rx_idle           <= rx_idle_reg;        
tx                <= tx_reg;             

go_rx_idle     <=                        sample_point and  sampled_bit and last_bit_of_inter_reg;
go_rx_id1      <=                        sample_point and  (not sampled_bit) and (rx_idle_reg or last_bit_of_inter_reg);
go_rx_rtr1     <= (not bit_de_stuff) and sample_point and  rx_id1  and bit_cnt_10;
go_rx_ide      <= (not bit_de_stuff) and sample_point and  rx_rtr1;
go_rx_id2      <= (not bit_de_stuff) and sample_point and  rx_ide  and sampled_bit;
go_rx_rtr2     <= (not bit_de_stuff) and sample_point and  rx_id2  and bit_cnt_17; 
go_rx_r1       <= (not bit_de_stuff) and sample_point and  rx_rtr2;
go_rx_r0       <= (not bit_de_stuff) and sample_point and (rx_ide  and ((not sampled_bit) or rx_r1));
go_rx_dlc      <= (not bit_de_stuff) and sample_point and  rx_r0;


go_rx_data     <= (not bit_de_stuff) and sample_point and  rx_dlc  and (bit_cnt_03) and  (sampled_bit   or   (data_len(0) or data_len(1) or data_len(2))) and (not remote_rq);
go_rx_crc      <= (not bit_de_stuff) and sample_point and (rx_dlc  and (bit_cnt_03) and ((((not sampled_bit) and  (not (data_len(0) or data_len(1) or data_len(2)))) or remote_rq) 
                                        or (rx_data and temp_sig)));  
go_rx_crc_lim  <= (not bit_de_stuff) and sample_point and  rx_crc  and (bit_cnt_14);
go_rx_ack      <=                   sample_point and  rx_crc_lim;
go_rx_ack_lim  <=                   sample_point and  rx_ack;
go_rx_eof      <=                   (sample_point and  rx_ack_lim)  or ((not reset_mode) and reset_mode_q);
go_rx_inter    <=                 ((sample_point and  rx_eof  and eof_cnt_06) or (error_frame_ended) or (overload_frame_ended)) and (not overload_needed);

go_error_frame <= (form_err or stuff_err or bit_err or ack_err or (crc_err and go_rx_eof));
error_frame_ended <= (error_cnt2_07) and tx_point;
overload_frame_ended <= (overload_cnt2_07) and tx_point;

go_overload_frame <= (   (((sample_point and  rx_eof and eof_cnt_06) or error_frame_ended or overload_frame_ended) and overload_needed) or 
                               (sample_point and (not sampled_bit) and rx_inter and bit_cnt_02)                                         or 
                               (sample_point and (not sampled_bit) and (error_cnt2_07 or overload_cnt2_07))
                      )
                           and (not overload_frame_blocked)
                           ;

go_crc_enable  <= hard_sync or go_tx;
rst_crc_enable <= go_rx_crc;

bit_de_stuff_set   <= go_rx_id1;
bit_de_stuff_reset <= go_rx_crc_lim or reset_mode or go_error_frame or go_overload_frame;

remote_rq <= ((not ide) and rtr1) or (ide and rtr2);
limited_data_len <= data_len when (data_len < "1000") else  X"8";

ack_err <= rx_ack and sample_point and sampled_bit and tx_state;
bit_err <= (tx_state or error_frame or overload_frame or rx_ack) and sample_point and (tx_reg_not_sample_bit) and (not bit_err_exc1) and (not bit_err_exc2) and (not bit_err_exc3) and (not bit_err_exc4) and (not bit_err_exc5);
bit_err_exc1 <= tx_state and arbitration_field and tx_reg;
bit_err_exc2 <= rx_ack and tx_reg;
bit_err_exc3 <= error_frame and node_error_passive and error_cnt1_less_than_07;
bit_err_exc4 <= (error_frame and (error_cnt1_07) and (not enable_error_cnt2)) or (overload_frame and (overload_cnt1_07) and (not enable_overload_cnt2));
bit_err_exc5 <= (error_frame and error_cnt2_07) or (overload_frame and overload_cnt2_07);

arbitration_field <= rx_id1 or rx_rtr1 or rx_ide or rx_id2 or rx_rtr2;

last_bit_of_inter_reg <= rx_inter and (bit_cnt_02);


-- Rx idle state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_idle_reg <= '0';
  elsif (reset_mode = '1' or go_rx_id1 = '1' or error_frame = '1') then
    rx_idle_reg <= '0' after Tp;
  elsif (go_rx_idle = '1') then
    rx_idle_reg <='1' after Tp;
  end if;
end if;    
end process;


-- Rx id1 state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_id1 <= '0';
  elsif (reset_mode = '1' or go_rx_rtr1 = '1' or error_frame = '1') then
    rx_id1 <='0' after Tp;
  elsif (go_rx_id1 = '1') then
    rx_id1 <='1' after Tp;
  end if;
end if;
end process;



-- Rx rtr1 state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_rtr1 <= '0';
  elsif (reset_mode = '1' or go_rx_ide = '1' or error_frame = '1') then
    rx_rtr1 <='0' after Tp;
  elsif (go_rx_rtr1 = '1') then
    rx_rtr1 <='1' after Tp;
  end if;
end if;
end process;


-- Rx ide state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_ide <= '0';
  elsif (reset_mode = '1' or go_rx_r0 = '1' or go_rx_id2 = '1' or error_frame = '1') then
    rx_ide <='0';
  elsif (go_rx_ide = '1') then
    rx_ide <='1';
  end if;
end if;
end process;


-- Rx id2 state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_id2 <= '0';
  elsif (reset_mode = '1' or go_rx_rtr2 = '1' or error_frame = '1') then
    rx_id2 <= '0' after Tp;
  elsif (go_rx_id2 = '1') then
    rx_id2 <= '1' after Tp;
  end if;
end if;
end process;


-- Rx rtr2 state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_rtr2 <= '0';
  elsif (reset_mode = '1' or go_rx_r1 = '1' or error_frame = '1') then
    rx_rtr2 <= '0' after Tp;
  elsif (go_rx_rtr2 = '1') then
    rx_rtr2 <= '1' after Tp;
  end if;
end if;
end process;


-- Rx r0 state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_r1 <= '0';
  elsif (reset_mode = '1' or go_rx_r0 = '1' or error_frame = '1') then
    rx_r1 <= '0' after Tp;
  elsif (go_rx_r1 = '1') then
    rx_r1 <= '1' after Tp;
  end if;
end if;
end process;


-- Rx r0 state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_r0 <= '0';
  elsif (reset_mode = '1' or go_rx_dlc = '1' or error_frame = '1') then
    rx_r0 <= '0' after Tp;
  elsif (go_rx_r0 = '1') then
    rx_r0 <= '1';
  end if;
end if;
end process;


-- Rx dlc state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_dlc <= '0';
  elsif (reset_mode = '1' or go_rx_data = '1' or go_rx_crc = '1' or error_frame = '1') then
    rx_dlc <= '0' after Tp;
  elsif (go_rx_dlc = '1') then
    rx_dlc <= '1' after Tp;
  end if;
end if;
end process;


-- Rx data state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_data <= '0';
  elsif (reset_mode = '1' or go_rx_crc = '1' or error_frame = '1') then
    rx_data <= '0' after Tp;
  elsif (go_rx_data = '1') then
    rx_data <= '1' after Tp;
  end if;
end if;
end process;


-- Rx crc state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_crc <= '0';
  elsif (reset_mode = '1' or go_rx_crc_lim = '1' or error_frame = '1') then
    rx_crc <= '0' after Tp;
  elsif (go_rx_crc = '1') then
    rx_crc <= '1' after Tp;
  end if;
end if;
end process;


-- Rx crc delimiter state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_crc_lim <= '0';
  elsif (reset_mode = '1' or go_rx_ack = '1' or error_frame = '1') then
    rx_crc_lim <= '0';
  elsif (go_rx_crc_lim = '1') then
    rx_crc_lim <= '1';
  end if;
end if;
end process;


-- Rx ack state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_ack <= '0';
  elsif (reset_mode = '1' or go_rx_ack_lim = '1' or error_frame = '1') then
    rx_ack <= '0';
  elsif (go_rx_ack = '1') then
    rx_ack <= '1';
  end if;
end if;
end process;


-- Rx ack delimiter state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_ack_lim <= '0';
  elsif (reset_mode = '1' or go_rx_eof = '1' or error_frame = '1') then
    rx_ack_lim <= '0' after Tp;
  elsif (go_rx_ack_lim = '1') then
    rx_ack_lim <= '1';
  end if;
end if;
end process;



-- Rx eof state
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_eof <= '0';
  elsif (go_rx_inter = '1' or error_frame = '1' or go_overload_frame = '1') then
    rx_eof <= '0' after Tp;
  elsif (go_rx_eof = '1') then
    rx_eof <= '1' after Tp;
  end if;
end if;
end process;



-- Interframe space
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rx_inter <= '0';
  elsif (go_rx_idle = '1' or go_rx_id1 = '1' or go_overload_frame = '1' or go_error_frame = '1') then
    rx_inter <= '0' after Tp;
  elsif (go_rx_inter = '1') then
    rx_inter <= '1' after Tp;
  end if;
end if;
end process;


-- ID register
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    id <= "00000000000000000000000000000";
  elsif (sample_point = '1' and (rx_id1 = '1' or rx_id2 = '1') and  bit_de_stuff = '0') then
    id <= id(27 downto 0)&sampled_bit after Tp;
  end if;
end if;
end process;


-- rtr1 bit
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rtr1 <= '0';
  elsif (sample_point = '1' and rx_rtr1 = '1' and bit_de_stuff = '0') then
    rtr1 <= sampled_bit after Tp;
  end if;
end if;
end process;



-- rtr2 bit
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    rtr2 <= '0';
  elsif (sample_point = '1' and rx_rtr2 = '1' and bit_de_stuff = '0') then
    rtr2 <= sampled_bit after Tp;
  end if;  
end if;
end process;


-- ide bit
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    ide <= '0';
  elsif (sample_point = '1' and rx_ide = '1' and bit_de_stuff = '0') then
    ide <= sampled_bit after Tp;
  end if;
end if;
end process;


-- Data length
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    data_len <= "0000";
  elsif (sample_point = '1' and rx_dlc = '1' and bit_de_stuff = '0') then
    data_len <= data_len(2 downto 0)& sampled_bit;
  end if;
end if;
end process;


-- Data
process(clk,rst)
begin
if(clk = '1' and clk'event) then
  if (rst = '1') then
    tmp_data <= X"00";
  elsif (sample_point = '1' and rx_data = '1' and bit_de_stuff = '0') then
    tmp_data <= tmp_data(6 downto 0)&sampled_bit;
  end if;
end if;
end process;


process(clk,rst)
begin
if(clk = '1' and clk'event) then