can_bsp.vhd

一个基于can_bus的虚拟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

entity can_bsp is
 port (
        clk:                    in std_logic;
        rst:                    in std_logic;
        sample_point:           in std_logic;
        sampled_bit:            in std_logic;
        sampled_bit_q:          in std_logic;
        tx_point:               in std_logic;
        hard_sync:              in std_logic;
        addr:                   in std_logic_vector(7 downto 0);
        data_out:               out std_logic_vector(7 downto 0);


        reset_mode:             in std_logic;
        acceptance_filter_mode: in std_logic;
        extended_mode:          in std_logic;


        release_buffer:         in std_logic;
        tx_request:             in std_logic;

        rx_idle:                out std_logic;
        transmitting:           out std_logic;
        last_bit_of_inter:      out std_logic;



        acceptance_code_0:      in std_logic_vector(7 downto 0);
        acceptance_mask_0:      in std_logic_vector(7 downto 0);


        acceptance_code_1:      in std_logic_vector(7 downto 0) ;
        acceptance_code_2:      in std_logic_vector(7 downto 0);
        acceptance_code_3:      in std_logic_vector(7 downto 0);


        acceptance_mask_1:      in std_logic_vector(7 downto 0);
        acceptance_mask_2:      in std_logic_vector(7 downto 0);
        acceptance_mask_3:      in std_logic_vector(7 downto 0);

        tx_data_0:              in std_logic_vector(7 downto 0);
        tx_data_1:              in std_logic_vector(7 downto 0);
        tx_data_2:              in std_logic_vector(7 downto 0);
        tx_data_3:              in std_logic_vector(7 downto 0);
        tx_data_4:              in std_logic_vector(7 downto 0);
        tx_data_5:              in std_logic_vector(7 downto 0);
        tx_data_6:              in std_logic_vector(7 downto 0);
        tx_data_7:              in std_logic_vector(7 downto 0);
        tx_data_8:              in std_logic_vector(7 downto 0);
        tx_data_9:              in std_logic_vector(7 downto 0);
        tx_data_10:             in std_logic_vector(7 downto 0);
        tx_data_11:             in std_logic_vector(7 downto 0);
        tx_data_12:             in std_logic_vector(7 downto 0);


        tx:                     out std_logic ;
        tx_oen:                 out std_logic);

end can_bsp;

architecture RTL of can_bsp is

component can_crc is
port ( 
        clk        : in  std_logic                     ;        
        data       : in  std_logic                     ;      
        enable     : in  std_logic                     ;    
        initialize : in  std_logic                     ;
                   
        crc        : out std_logic_vector(14 downto 0));       
end component;
        
component can_acf is
 port ( 
       clk:                    in std_logic;
       rst:                    in std_logic;
       id:                     in std_logic_vector(28 downto 0);
       reset_mode:             in std_logic;
       acceptance_filter_mode: in std_logic;
       extended_mode:          in std_logic;

       acceptance_code_0: in std_logic_vector(7 downto 0);
       acceptance_code_1: in std_logic_vector(7 downto 0);
       acceptance_code_2: in std_logic_vector(7 downto 0);
       acceptance_code_3: in std_logic_vector(7 downto 0);
       acceptance_mask_0: in std_logic_vector(7 downto 0);
       acceptance_mask_1: in std_logic_vector(7 downto 0);
       acceptance_mask_2: in std_logic_vector(7 downto 0);
       acceptance_mask_3: in std_logic_vector(7 downto 0);
      
       go_rx_crc_lim:     in std_logic;
       go_rx_inter:       in std_logic;
       go_error_frame:    in std_logic;
       data0:             in std_logic_vector(7 downto 0);
       data1:             in std_logic_vector(7 downto 0);
       rtr1:              in std_logic;
       rtr2:              in std_logic;
       ide:               in std_logic;
       no_byte0:          in std_logic;
       no_byte1:          in std_logic;

       id_ok:             out std_logic);
end component;

component can_fifo is
port ( 

     clk            : in std_logic                     ;
     rst            : in std_logic                     ;
     wr             : in std_logic                     ;
     data_in        : in std_logic_vector(7 downto 0)  ;
     addr           : in std_logic_vector(7 downto 0)  ;
     reset_mode     : in std_logic                     ;
     release_buffer : in std_logic                     ;
     extended_mode  : in std_logic                     ;
    
     data_out       : out std_logic_vector(7 downto 0));
end component;

component can_ibo is
port( 
  di: in  std_logic_vector(7 downto 0) ;
  do: out std_logic_vector(7 downto 0));
end component;

signal reset_mode_q       : std_logic;
signal bit_cnt            : std_logic_vector(5  downto 0);

signal data_len           : std_logic_vector(3  downto 0);
signal id                 : std_logic_vector(28 downto 0);
signal bit_stuff_cnt      : std_logic_vector(2  downto 0);
signal bit_stuff_cnt_tx   : std_logic_vector(2  downto 0);
signal tx_point_q         : std_logic;


signal rx_id1             : std_logic;
signal rx_rtr1            : std_logic;
signal rx_ide             : std_logic;
signal rx_id2             : std_logic;
signal rx_rtr2            : std_logic;
signal rx_r1              : std_logic;
signal rx_r0              : std_logic;
signal rx_dlc             : std_logic;
signal rx_data            : std_logic;
signal rx_crc             : std_logic;
signal rx_crc_lim         : std_logic;
signal rx_ack             : std_logic;
signal rx_ack_lim         : std_logic;
signal rx_eof             : std_logic;
signal rx_inter           : std_logic;

signal rtr1               : std_logic;
signal ide                : std_logic;
signal rtr2               : std_logic;
signal crc_in             : std_logic_vector(14 downto 0);

signal tmp_data           : std_logic_vector(7  downto 0);

type   fifo is array(7 downto 0) of std_logic_vector(7 downto 0);
signal tmp_fifo           : fifo;

signal write_data_to_tmp_fifo: std_logic;
signal byte_cnt           : std_logic_vector(2 downto 0);
signal bit_stuff_cnt_en   : std_logic;
signal crc_enable         : std_logic;

signal eof_cnt            : std_logic_vector(2 downto 0);
signal passive_cnt        : std_logic_vector(2 downto 0);



signal error_frame        : std_logic;
signal error_frame_q      : std_logic;
signal enable_error_cnt2  : std_logic;
signal error_cnt1         : std_logic_vector(2 downto 0);
signal error_cnt2         : std_logic_vector(2 downto 0);
signal delayed_dominant_cnt: std_logic_vector(2 downto 0);
signal enable_overload_cnt2: std_logic;
signal overload_frame     : std_logic;
signal overload_frame_blocked: std_logic;
signal overload_cnt1      : std_logic_vector(2 downto 0);
signal overload_cnt2      : std_logic_vector(2 downto 0);

signal crc_err            : std_logic;

signal priority_lost      : std_logic;
signal tx_q               : std_logic;

signal need_to_tx         : std_logic;   
signal data_cnt           : std_logic_vector(3 downto 0);    
signal header_cnt         : std_logic_vector(2 downto 0);   
signal wr_fifo            : std_logic;      
signal data_for_fifo      : std_logic_vector(7 downto 0);

signal tx_pointer         : std_logic_vector(5 downto 0);
signal tx_bit             : std_logic;
signal tx_state           : std_logic;
signal transmitter        : std_logic;
signal finish_msg         : std_logic;

signal rx_err_cnt         : std_logic_vector(9 downto 0);
signal tx_err_cnt         : std_logic_vector(9 downto 0);
signal rx_err_cnt_blocked : std_logic;
signal recessive_cnt      : std_logic_vector(10 downto 0);

signal node_error_passive : std_logic;
signal node_bus_off       : std_logic;
signal ack_err_latched    : std_logic;
signal bit_err_latched    : std_logic;
signal stuff_err_latched  : std_logic;
signal form_err_latched   : std_logic;
signal rule5              : std_logic;
signal rule3_exc1_1       : std_logic;
signal rule3_exc1_2       : std_logic;
signal rule3_exc2         : std_logic;
signal suspend            : std_logic;
signal susp_cnt_en        : std_logic;
signal susp_cnt           : std_logic_vector(2 downto 0);
signal go_error_frame_q   : std_logic;
signal error_flag_over_blocked: std_logic;

signal bit_de_stuff       : std_logic;
signal bit_de_stuff_tx    : std_logic;



signal go_rx_idle         : std_logic;
signal go_rx_id1          : std_logic;
signal go_rx_rtr1         : std_logic;
signal go_rx_ide          : std_logic;
signal go_rx_id2          : std_logic;
signal go_rx_rtr2         : std_logic;
signal go_rx_r1           : std_logic;
signal go_rx_r0           : std_logic;
signal go_rx_dlc          : std_logic;
signal go_rx_data         : std_logic;
signal go_rx_crc          : std_logic;
signal go_rx_crc_lim      : std_logic;
signal go_rx_ack          : std_logic;
signal go_rx_ack_lim      : std_logic;
signal go_rx_eof          : std_logic;
signal go_error_frame     : std_logic;
signal go_overload_frame  : std_logic;
signal go_rx_inter        : std_logic;

signal go_crc_enable      : std_logic;
signal rst_crc_enable     : std_logic;

signal bit_de_stuff_set   : std_logic;
signal bit_de_stuff_reset : std_logic;

signal go_early_tx        : std_logic;
signal go_tx              : std_logic;

signal calculated_crc     : std_logic_vector(14 downto 0);
signal r_calculated_crc   : std_logic_vector(15 downto 0);
signal remote_rq          : std_logic;
signal limited_data_len   : std_logic_vector(3 downto 0);
signal form_err           : std_logic;
signal set_form_error     : std_logic;

signal error_frame_ended  : std_logic;
signal overload_frame_ended: std_logic;
signal bit_err            : std_logic;
signal ack_err            : std_logic;
signal stuff_err          : std_logic;
                                    
signal overload_needed    : std_logic := '0';  
                                    

signal id_ok              : std_logic;                
signal no_byte0           : std_logic;             
signal no_byte1           : std_logic;            

signal header_len         : std_logic_vector(2 downto 0);
signal storing_header     : std_logic;
signal limited_data_len_minus1: std_logic_vector(3 downto 0);
signal reset_wr_fifo      : std_logic;
signal err                : std_logic;

signal tx_successful      : std_logic;
signal recessive_cnt_ok   : std_logic;
signal arbitration_field  : std_logic;

signal basic_chain        : std_logic_vector(18 downto 0);
signal basic_chain_data   : std_logic_vector(63 downto 0);
signal extended_chain_std : std_logic_vector(18 downto 0);
signal extended_chain_ext : std_logic_vector(38 downto 0);
signal extended_chain_data: std_logic_vector(63 downto 0);

signal rst_tx_pointer     : std_logic;

signal r_tx_data_0        :  std_logic_vector(7 downto 0);
signal r_tx_data_1        :  std_logic_vector(7 downto 0);
signal r_tx_data_2        :  std_logic_vector(7 downto 0);
signal r_tx_data_3        :  std_logic_vector(7 downto 0);
signal r_tx_data_4        :  std_logic_vector(7 downto 0);
signal r_tx_data_5        :  std_logic_vector(7 downto 0);
signal r_tx_data_6        :  std_logic_vector(7 downto 0);
signal r_tx_data_7        :  std_logic_vector(7 downto 0);
signal r_tx_data_8        :  std_logic_vector(7 downto 0);
signal r_tx_data_9        :  std_logic_vector(7 downto 0);
signal r_tx_data_10       : std_logic_vector(7 downto 0);
signal r_tx_data_11       : std_logic_vector(7 downto 0);
signal r_tx_data_12       : std_logic_vector(7 downto 0);

signal send_ack           : std_logic;
signal bit_err_exc1       : std_logic;
signal bit_err_exc2       : std_logic;
signal bit_err_exc3       : std_logic;
signal bit_err_exc4       : std_logic;
signal bit_err_exc5       : std_logic;
signal error_flag_over    : std_logic;
signal overload_flag_over : std_logic;          

signal last_bit_of_inter_reg: std_logic;
signal rx_idle_reg        : std_logic;
signal tx_reg             : std_logic;

signal bit_cnt_10: std_logic;
signal bit_cnt_17: std_logic;
signal bit_cnt_14: std_logic;
signal bit_cnt_03: std_logic;
signal bit_cnt_02: std_logic;

signal eof_cnt_06              :std_logic;
signal eof_cnt_less_06         :std_logic;
signal error_cnt1_07           :std_logic;
signal error_cnt2_07           :std_logic;
signal overload_cnt2_07        :std_logic;
signal overload_cnt1_07        :std_logic;
signal overload_cnt1_less_07   :std_logic;
signal bit_cnt_less_than_02    :std_logic;
signal error_cnt1_less_than_07 :std_logic;
signal tx_reg_not_sample_bit   :std_logic;
signal temp_sig                :std_logic;        
signal data_len_less_01        :std_logic;
signal data_len_less_02        :std_logic;  
signal data_len_less_08        :std_logic;  
signal passive_cnt_05          :std_logic;
signal passive_cnt_less_05     :std_logic;
signal error_cnt1_less_06      :std_logic;
signal overload_cnt1_less_06   :std_logic;
signal enable_sig              :std_logic;  
signal initialize_sig          :std_logic;
signal di_sig                  :std_logic_vector(7 downto 0);

constant Tp                    :time := 1 ns;                    

begin

eof_cnt_06              <= '1' when eof_cnt       = "110" else '0'; 
eof_cnt_less_06         <= '1' when eof_cnt       < "110" else '0'; 
error_cnt1_07           <= '1' when error_cnt1    = "111" else '0';
error_cnt1_less_06      <= '1' when error_cnt1    < "110" else '0';
error_cnt2_07           <= '1' when error_cnt2    = "111" else '0';
overload_cnt2_07        <= '1' when overload_cnt2 = "111" else '0';
overload_cnt1_07        <= '1' when overload_cnt1 = "111" else '0';
overload_cnt1_less_07   <= '1' when (overload_cnt1< "111")else '0';
overload_cnt1_less_06   <= '1' when (overload_cnt1< "110")else '0';
bit_cnt_less_than_02    <= '1' when (bit_cnt < "000010")  else '0';
error_cnt1_less_than_07 <= '1' when (error_cnt1 < "111")  else '0';
tx_reg_not_sample_bit   <= '1' when tx_reg /= sampled_bit else '0';  

bit_cnt_10 <= '1' when bit_cnt = "001010" else '0';  -- 10
bit_cnt_17 <= '1' when bit_cnt = "010001" else '0';  -- 17
bit_cnt_02 <= '1' when bit_cnt = "000010" else '0';  -- 02
bit_cnt_03 <= '1' when bit_cnt = "000011" else '0';  -- 03
bit_cnt_14 <= '1' when bit_cnt = "001110" else '0';  -- 14

temp_sig <= '1' when (bit_cnt = (limited_data_len(0)&"000" - conv_std_logic_vector(1,4)) ) else '0';

data_len_less_01 <= '1' when data_len < X"1" else '0';
data_len_less_02 <= '1' when data_len < X"2" else '0';
data_len_less_08 <= '1' when data_len < X"8" else '0';

passive_cnt_05        <= '1' when passive_cnt = "101" else '0';
passive_cnt_less_05   <= '1' when passive_cnt < "101" else '0';