can_crc.vhd

一个基于can_bus的虚拟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

entity can_crc is
port ( 
        clk        : in  std_logic                     ;        
        data       : in  std_logic                     ;      
        enable     : in  std_logic                     ;    
        initialize : in  std_logic                     ;
                   
        crc        : out std_logic_vector(14 downto 0));       
end can_crc;

architecture RTL of can_crc is

constant Tp       : time := 1 ns;


signal   crc_reg      : std_logic_vector(14 downto 0);

signal   crc_next : std_logic;
signal   crc_tmp  : std_logic_vector(14 downto 0);

begin

crc_next <= data xor crc_reg(14);
crc_tmp  <= crc_reg(13 downto 0)&'0';

process(clk)
begin
if (clk = '1' and clk'event) then
  if(initialize = '1') then
    crc_reg <= (others => '0') after Tp;
  elsif (enable = '1') then
     if (crc_next = '1') then
        crc_reg <=  crc_tmp xor "100010110011001" after Tp; -- X"4599"
      else
        crc_reg <=  crc_tmp after Tp;
      end if;
  end if;    
end if;
end process;

crc <= crc_reg;
 
end RTL;