can_testbench.v

一个基于can_bus的虚拟程序

        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC DELIM
        send_bit(1);  // ACK            ack error
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // INTER
        send_bit(1);  // INTER
        send_bit(1);  // INTER
    end // repeat

    repeat (20)
    begin
        send_bit(0);  // SOF
        send_bit(1);  // ID
        send_bit(1);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(0);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(1);  // RTR
        send_bit(0);  // IDE
        send_bit(0);  // r0
        send_bit(0);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC DELIM
        send_bit(1);  // ACK            ack error
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(0);  // ERROR
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // ERROR DELIM
        send_bit(1);  // INTER
        send_bit(1);  // INTER
        send_bit(1);  // INTER
        send_bit(1);  // SUSPEND
        send_bit(1);  // SUSPEND
        send_bit(1);  // SUSPEND
        send_bit(1);  // SUSPEND
        send_bit(1);  // SUSPEND
        send_bit(1);  // SUSPEND
        send_bit(1);  // SUSPEND
        send_bit(1);  // SUSPEND
   end // repeat

    repeat (20)
    begin
        send_bit(0);  // SOF
        send_bit(1);  // ID
        send_bit(1);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(0);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(1);  // RTR
        send_bit(0);  // IDE
        send_bit(0);  // r0
        send_bit(0);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC DELIM
        send_bit(0);  // ACK
        send_bit(1);  // ACK DELIM
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // INTER
        send_bit(1);  // INTER
        send_bit(1);  // INTER
   end // repeat

    repeat (128 * 11)
    begin
        send_bit(1);
    end // repeat

    tx_request;




      end
    
    
    join

    read_receive_buffer;
    release_rx_buffer;





    read_receive_buffer;
    release_rx_buffer;
    read_receive_buffer;

    #4000000;

  end
endtask



task send_frame;    // CAN IP core sends frames
  begin

    if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
      begin

        // Writing TX frame information + identifier + data
        write_register(8'd16, 8'h12);
        write_register(8'd17, 8'h34);
        write_register(8'd18, 8'h56);
        write_register(8'd19, 8'h78);
        write_register(8'd20, 8'h9a);
        write_register(8'd21, 8'hbc);
        write_register(8'd22, 8'hde);
        write_register(8'd23, 8'hf0);
        write_register(8'd24, 8'h0f);
        write_register(8'd25, 8'hed);
        write_register(8'd26, 8'hcb);
        write_register(8'd27, 8'ha9);
        write_register(8'd28, 8'h87);
      end
    else
      begin
        write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
        write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
        write_register(8'd12, 8'h56); // data byte 1
        write_register(8'd13, 8'h78); // data byte 2
        write_register(8'd14, 8'h9a); // data byte 3
        write_register(8'd15, 8'hbc); // data byte 4
        write_register(8'd16, 8'hde); // data byte 5
        write_register(8'd17, 8'hf0); // data byte 6
        write_register(8'd18, 8'h0f); // data byte 7
        write_register(8'd19, 8'hed); // data byte 8
      end

  
    fork
      begin
        $display("\n\nStart receiving data from CAN bus");
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc

      end

      begin
        tx_request;
      end

      begin
        // Transmitting acknowledge
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
        #1 rx = 0;
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
        #1 rx = 1;
      end

    join

    read_receive_buffer;
    release_rx_buffer;
    release_rx_buffer;
    read_receive_buffer;
    release_rx_buffer;
    read_receive_buffer;
    release_rx_buffer;
    read_receive_buffer;
    release_rx_buffer;
    read_receive_buffer;

    #200000;

    read_receive_buffer;

  end
endtask



task test_empty_fifo;
  begin
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc

    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc

    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
  end
endtask



task test_empty_fifo_ext;
  begin
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
    
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc

    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
  end
endtask



task test_full_fifo;
  begin
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;

    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
    read_receive_buffer;
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h1, 15'h1ccf); // mode, rtr, id, length, crc
    read_receive_buffer;
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h2, 15'h73f4); // mode, rtr, id, length, crc
    fifo_info;
    read_receive_buffer;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h4, 15'h37da); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h5, 15'h7e15); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h6, 15'h39cf); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    read_overrun_info(0, 15);

    release_rx_buffer;
    release_rx_buffer;
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    read_overrun_info(0, 15);
    $display("\n\n");

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;

    release_rx_buffer;
    read_receive_buffer;
    fifo_info;