can_testbench.v

一个基于can_bus的虚拟程序

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_testbench.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       [e-mail]                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: can_testbench.v,v $
// Revision 1.22  2003/02/11 00:57:19  mohor
// Wishbone interface added.
//
// Revision 1.21  2003/02/09 18:40:23  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.20  2003/02/09 02:24:11  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.19  2003/02/04 17:24:33  mohor
// Backup.
//
// Revision 1.18  2003/02/04 14:34:45  mohor
// *** empty log message ***
//
// Revision 1.17  2003/01/31 01:13:31  mohor
// backup.
//
// Revision 1.16  2003/01/16 13:36:14  mohor
// Form error supported. When receiving messages, last bit of the end-of-frame
// does not generate form error. Receiver goes to the idle mode one bit sooner.
// (CAN specification ver 2.0, part B, page 57).
//
// Revision 1.15  2003/01/15 21:05:06  mohor
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
//
// Revision 1.14  2003/01/15 14:40:16  mohor
// RX state machine fixed to receive "remote request" frames correctly. No
// data bytes are written to fifo when such frames are received.
//
// Revision 1.13  2003/01/15 13:16:42  mohor
// When a frame with "remote request" is received, no data is stored to
// fifo, just the frame information (identifier, ...). Data length that
// is stored is the received data length and not the actual data length
// that is stored to fifo.
//
// Revision 1.12  2003/01/14 17:25:03  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.11  2003/01/14 12:19:29  mohor
// rx_fifo is now working.
//
// Revision 1.10  2003/01/10 17:51:28  mohor
// Temporary version (backup).
//
// Revision 1.9  2003/01/09 21:54:39  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.8  2003/01/08 02:09:43  mohor
// Acceptance filter added.
//
// Revision 1.7  2002/12/28 04:13:53  mohor
// Backup version.
//
// Revision 1.6  2002/12/27 00:12:48  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.5  2002/12/26 16:00:29  mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.4  2002/12/26 01:33:01  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:12  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:16:54  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"

module can_testbench();



parameter Tp = 1;
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);



reg         wb_clk_i;
reg         wb_rst_i;
reg   [7:0] wb_dat_i;
wire  [7:0] wb_dat_o;
reg         wb_cyc_i;
reg         wb_stb_i;

reg         wb_we_i;
reg   [7:0] wb_adr_i;
reg         clk;
reg         rx;
wire        tx;
wire        tx_oen;
wire        wb_ack_o;

wire        tx_3st;
wire        rx_and_tx;

integer     start_tb;
reg   [7:0] tmp_data;
reg         delayed_tx;
reg         tx_bypassed;


// Instantiate can_top module
can_top i_can_top
( 
  .wb_clk_i(wb_clk_i),
  .wb_rst_i(wb_rst_i),
  .wb_dat_i(wb_dat_i),
  .wb_dat_o(wb_dat_o),
  .wb_cyc_i(wb_cyc_i),
  .wb_stb_i(wb_stb_i),
  .wb_we_i(wb_we_i),
  .wb_adr_i(wb_adr_i),
  .wb_ack_o(wb_ack_o),
  .clk(clk),
  .rx(rx_and_tx),
  .tx(tx),
  .tx_oen(tx_oen)
);

assign tx_3st = tx_oen? 1'bz : tx;


// Generate wishbone clock signal 10 MHz
initial
begin
  wb_clk_i=0;
  forever #50 wb_clk_i = ~wb_clk_i;
end


// Generate clock signal 24 MHz
initial
begin
  clk=0;
  forever #20 clk = ~clk;
end


initial
begin
  start_tb = 0;
  wb_dat_i = 'hz;
  wb_cyc_i = 0;
  wb_stb_i = 0;
  wb_we_i = 'hz;
  wb_adr_i = 'hz;
  rx = 1;
  wb_rst_i = 1;
  #200 wb_rst_i = 0;
  #200 initialize_fifo;
  #200 start_tb = 1;
  tx_bypassed = 0;
end




// Generating delayed tx signal (CAN transciever delay)
always
begin
  wait (tx_3st);
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
  #1 delayed_tx = tx_3st;
  wait (~tx_3st);
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
  #1 delayed_tx = tx_3st;
end

//assign rx_and_tx = rx & delayed_tx;   FIX ME !!!
assign rx_and_tx = rx & (delayed_tx | tx_bypassed);


// Main testbench
initial
begin
  wait(start_tb);

  // Set bus timing register 0
  write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});

  // Set bus timing register 1
  write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});



  // Set Clock Divider register
  write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0});    // Setting the normal mode (not extended)
 
  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
      // Set Acceptance Code and Acceptance Mask registers
      write_register(8'd16, 8'ha6); // acceptance code 0
      write_register(8'd17, 8'hb0); // acceptance code 1
      write_register(8'd18, 8'h12); // acceptance code 2
      write_register(8'd19, 8'h30); // acceptance code 3
      write_register(8'd20, 8'h0); // acceptance mask 0
      write_register(8'd21, 8'h0); // acceptance mask 1
      write_register(8'd22, 8'h00); // acceptance mask 2
      write_register(8'd23, 8'h00); // acceptance mask 3
    end
  else
    begin
      // Set Acceptance Code and Acceptance Mask registers
//      write_register(8'd4, 8'ha6); // acceptance code
      write_register(8'd4, 8'h08); // acceptance code
      write_register(8'd5, 8'h0f); // acceptance mask
    end
  
  #10;
  repeat (1000) @ (posedge clk);
  
  // Switch-off reset mode
  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});

  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
                                  // This difference is resynchronized later.

  // After exiting the reset mode
  repeat (7) send_bit(1);         // Sending EOF
  repeat (3) send_bit(1);         // Sending Interframe

//  test_synchronization;



  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
//      test_empty_fifo_ext;    // test currently switched off
      test_full_fifo_ext;     // test currently switched on
//      send_frame_ext;         // test currently switched off
    end
  else
    begin
//      test_empty_fifo;    // test currently switched off
      test_full_fifo;     // test currently switched on
//      send_frame;         // test currently switched off
//      manual_frame;         // test currently switched off
    end


  $display("CAN Testbench finished !");
  $stop;
end


task manual_frame;    // Testbench sends a frame
  begin
/*
    begin

      $display("\n\nTestbench sends a frame bit by bit");
      send_bit(0);  // SOF
      send_bit(1);  // ID
      send_bit(1);  // ID
      send_bit(1);  // ID
      send_bit(0);  // ID
      send_bit(1);  // ID
      send_bit(0);  // ID
      send_bit(0);  // ID
      send_bit(0);  // ID
      send_bit(1);  // ID
      send_bit(0);  // ID
      send_bit(1);  // ID
      send_bit(1);  // RTR
      send_bit(0);  // IDE
      send_bit(0);  // r0
      send_bit(0);  // DLC
      send_bit(1);  // DLC
      send_bit(0);  // DLC
      send_bit(0);  // DLC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(0);  // CRC
      send_bit(0);  // CRC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(1);  // CRC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(1);  // CRC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(0);  // CRC          // error
      send_bit(1);  // CRC DELIM
      send_bit(0);  // ACK
      send_bit(1);  // ACK DELIM
      send_bit(0);  // EOF        // error comes here
      send_bit(0);  // EOF        // error comes here

//tx_bypassed=1;
      send_bit(0);  // EOF        // error comes here
//tx_bypassed=0;

      send_bit(0);  // EOF        // error comes here
      send_bit(0);  // EOF        // error comes here
      send_bit(0);  // EOF        // error comes here
      send_bit(1);  // EOF        // delimiter
      send_bit(1);  // INTER      // delimiter
      send_bit(1);  // INTER      // delimiter
      send_bit(1);  // INTER      // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(0);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE
      send_bit(1);  // IDLE
      send_bit(1);  // IDLE

    end
*/
// tx_bypassed=1;

  
    write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
    write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
    write_register(8'd12, 8'h00); // data byte 1
    write_register(8'd13, 8'h00); // data byte 2
    write_register(8'd14, 8'h00); // data byte 3
    write_register(8'd15, 8'h00); // data byte 4
    write_register(8'd16, 8'h00); // data byte 5
    write_register(8'd17, 8'h00); // data byte 6
    write_register(8'd18, 8'h00); // data byte 7
    write_register(8'd19, 8'h00); // data byte 8

    fork
      begin
        tx_request;
      end

      begin
        #520;

    repeat (16)
    begin
        send_bit(0);  // SOF
        send_bit(1);  // ID
        send_bit(1);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(0);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(1);  // RTR
        send_bit(0);  // IDE
        send_bit(0);  // r0
        send_bit(0);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC