can_register.vhd

一个基于can_bus的虚拟程序

library ieee;
use ieee.std_logic_1164.all;

entity can_register is
generic(
         WIDTH: integer := 8
        );
port        
(
      data_in  : in std_logic_vector(WIDTH-1 downto 0);
      we       : in std_logic;
      clk      : in std_logic;

      data_out :  out std_logic_vector(WIDTH-1 downto 0)
);
end can_register;

architecture RTL of can_register is

signal data_out_reg: std_logic_vector(WIDTH-1 downto 0);

begin

process(clk)
begin
if(clk = '1' and clk'event) then
  if (we = '1') then                 -- write
    data_out_reg <= data_in after 1 ns;
  end if;
end if;
end process;

data_out <= data_out_reg;

end RTL;