📄 pcipost.asm
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extrn E000_64k_Shadow_R:Near
extrn C000_Shadow_RW:near ;chipset.asm
extrn C000_Shadow_R:near ;chipset.asm
extrn C800_Shadow:near ;chipset.asm
extrn CC00_Shadow:near ;chipset.asm
extrn D000_Shadow:near ;chipset.asm
extrn D400_Shadow:near ;chipset.asm
extrn D800_Shadow:near ;chipset.asm
extrn DC00_Shadow:near ;chipset.asm
extrn PCI_SLOT_CFG:near ;chipset.asm
extrn Ct_Shadow_Unit:Near ;pcichip.asm
extrn Ct_C8_To_DF_RW:Near ;pcichip.asm
extrn Ct_C8_To_DF_R:Near ;pcichip.asm
extrn Ct_PCI_Info:Near ;pcichip.asm
extrn Ct_Special_PCI_Device:Near ;pcichip.asm
extrn Ct_Set_PciIrq:near ;pcichip.asm
extrn IrqRout_Table:near ;pcichip.asm
ifndef NEW_PNP_SETUP
extrn PciIrq_Item:near ;pcichip.asm
endif ;NEW_PNP_SETUP
extrn Ct_Disable_Shadow:Near ;pcichip.asm
;R82 ifdef CT_SHADOW_RW_HOOK_SUPPORT
extrn Ct_Shadow_R:near ;pcichip.asm
extrn Ct_Shadow_RW:near ;pcichip.asm
;R82 endif ;CT_SHADOW_RW_HOOK_SUPPORT
ifndef NO_PCI_IDE_CARD
extrn PCI_IDE_IRQ:near ;pcifeat.asm
extrn First_IDE_INT:near ;pcifeat.asm
extrn Second_IDE_INT:near ;pcifeat.asm
endif ;NO_PCI_IDE_CARD
ifndef NO_PCI_IDE_2ND_CONTROL
extrn Second_IDE_channel:near ;bfeature.asm
endif ;NO_PCI_IDE_2ND_CONTROL
extrn Ct_PCI_VGA_IDSEL:near ;pcichip.asm
ifdef CT_SPEICAL_PCI_VGA
extrn Set_Ct_For_PciVga:near
endif ;CT_SPEICAL_PCI_VGA
extrn Ct_Special_Copy_PCI_VGA:near
ifdef SPECIAL_PCI_IDE_PRG
extrn CT_PRI_PCI_IDE_PRG:near ;pcichip.asm
extrn CT_SEC_PCI_IDE_PRG:near ;pcichip.asm
endif ;SPECIAL_PCI_IDE_PRG
ifndef No_C8_DF_Shadow_Item ;R27
extrn C800_Item:near
extrn CC00_Item:near
extrn D000_Item:near
extrn D400_Item:near
extrn D800_Item:near
extrn DC00_Item:near
endif ;No_C8_DF_Shadow_Item ;R27
ifdef Combined_Other_PCI_ROM
extrn Ct_If_Combined_ROM_Needed:near
endif ;Combined_Other_PCI_ROM
ifdef MULTI_HOST_BRIDGE
extrn Ct_Set_Mult_PciBus:near
endif ;MULTI_HOST_BRIDGE
extrn GDTR1:fword
extrn code1_dt:near
extrn data1_dt:near
extrn data1_index:abs
extrn fProc_Pci_IO_Mem_Init:far
IF MSIRQROUT_SUPPORT
extrn MsPciIrqTbl:Near
ENDIF ;MSIRQROUT_SUPPORT
extrn PciIrqTbl_Size:Near
extrn IRQ_REQ_BUF:Near
extrn IRQ_REQ_BUF_PTR:Near
extrn fProc_PciRom_Before_Init:Far
extrn POST_decompress:near
extrn A20_On:Near
extrn A20_Off:Near
;R72 ifdef PNP_BIOS
;R72 extrn fProc_Reserve_Irq_For_PciBootDev:far ;R04
;R72 endif; PNP_BIOS
;R36 - start
ifdef RAID_BOOT_OPTION
extrn RaidBoot_Item:near
endif; RAID_BOOT_OPTION
;R36 - end
;R91A ifdef PciLanROM_Control ;R91
;R91A extrn LAN_COMMAND_WORD:word ;R91
;R91A endif ;PciLanROM_Control ;R91
endif ;PCI_BUS
extrn BootEntryTbl:near ;R96
extrn BootEntryEnd:near ;R96
extrn R_Mod_Ck:near ;R23
extrn F_C000_Shadow_R:near ;R82
DGROUP GROUP FCODE
FCODE SEGMENT USE16 PARA PUBLIC 'CODE'
ASSUME CS:DGROUP
ifdef PCI_BUS
;[]==============================================================[]
;
;Note : Don't destroy following codes , because it will be executed
; while warm booting
;
;Reset_PciMaster:
; Clear bit 2 (master bit ) of PCI command register
;
;Saves: all
;
;Input : none
;
;Output: None
;
;[]==============================================================[]
public Reset_PciMaster
Reset_PciMaster proc near
ifndef PCI_RESET_SUPPORT
pushad
xor bh, bh ;start from bus 0
Scan_Nxt_BusMs:
xor cx, cx ;start from devic 0 , func. 0
Scan_Nxt_Master:
ifdef Cx5510_PCI_REG
cmp ch, Cx5510_PCI_REG ;if Cyrix Cx5510 chipset
je Next_Dev ;
endif; Cx5510_PCI_REG
xor cl, cl
call AGet_CfgSpace_Word ;get vendor ID
cmp ax, -1 ;legal vendor ?
je Next_Dev
mov cl, 4
call AGet_CfgSpace_Byte ;get command register
and al, NOT 04H ;disable master bit
call ASet_CfgSpace_Byte ;Set command register
mov cl, 0bh
call AGet_CfgSpace_Byte ;get class code
cmp al, 02 ;is PCI LAN ?
jne No_PCI_LAN
mov cl, 04h
xor al, al
call ASet_CfgSpace_Byte ;clear command register.
No_PCI_LAN:
Next_Dev:
call Get_Nxt_Device ;CH return next device to do
jnc Scan_Nxt_Master
inc bh ;next bus
cmp bh, 4 ;total 4 buses
jb Scan_Nxt_BusMs
popad
endif; PCI_RESET_SUPPORT
ret
Reset_PciMaster endp
ifndef PCI_RESET_SUPPORT
;[]================================================================[]
;Get_Next_Device:
; This routine is used to get next device no to treat
;Input : CH - Slot identification Number
;Output : NC : CH - Next Slot ID numbuer
; CF : All slot & function spaces has scanned
;[]================================================================[]
ALIGN 4
Get_Nxt_Device proc near
test ch, 07h ;alread a multi-function space?
jnz @F ;yes, go point to next function
mov cl, 0Eh ;read header type
call AGet_CfgSpace_Byte ;read header type
test al, 80H ;multi-function support?
jnz @F ;yes, multi-function card!
and ch, NOT 111B ;mask function bits ;R57
add ch, 7 ;point to next device!
@@:
add ch, 1 ;point to next function space
jc @F ;already overflow!
ifdef CONFIG_MECHANISM_1
cmp ch, (31 SHL 3) ;exceed maximum device?
else ;CONFIG_MECHANISM_1
cmp ch, (15 SHL 3) ;exceed maximum device?
endif ;CONFIG_MECHANISM_1
ja @F ;yes, tell caller error!
clc ;success return
ret
@@:
stc ;error return
ret
Get_Nxt_Device endp
endif; PCI_RESET_SUPPORT
;[]================================================================[]
;[]================================================================[]
Public fProc_Get_CfgSpace_Byte
fProc_Get_CfgSpace_Byte Proc Far
call Get_CfgSpace_Byte
retf
fProc_Get_CfgSpace_Byte Endp
Get_CfgSpace_Byte Proc Near
push bx
mov bh, CURRENT_BUS_NO[bp]
call AGet_CfgSpace_Byte
pop bx
ret
Get_CfgSpace_Byte Endp
;-----------------------
;-----------------------
Public fProc_Get_CfgSpace_Word
fProc_Get_CfgSpace_Word Proc Far
call Get_CfgSpace_Word
retf
fProc_Get_CfgSpace_Word Endp
Get_CfgSpace_Word Proc Near
push bx
mov bh, CURRENT_BUS_NO[bp]
call AGet_CfgSpace_Word
pop bx
ret
Get_CfgSpace_Word Endp
;-----------------------
;-----------------------
Public fProc_Get_CfgSpace_Dword
fProc_Get_CfgSpace_Dword Proc Far
call Get_CfgSpace_Dword
retf
fProc_Get_CfgSpace_Dword Endp
Get_CfgSpace_Dword Proc Near
push bx
mov bh, CURRENT_BUS_NO[bp]
call AGet_CfgSpace_Dword
pop bx
ret
Get_CfgSpace_Dword Endp
;-----------------------
;-----------------------
Public fProc_Set_CfgSpace_Byte
fProc_Set_CfgSpace_Byte Proc Far
call Set_CfgSpace_Byte
retf
fProc_Set_CfgSpace_Byte Endp
Set_CfgSpace_Byte Proc Near
push bx
mov bh, CURRENT_BUS_NO[bp]
call ASet_CfgSpace_Byte
pop bx
ret
Set_CfgSpace_Byte Endp
;-----------------------
;-----------------------
Public fProc_Set_CfgSpace_Word
fProc_Set_CfgSpace_Word Proc Far
call Set_CfgSpace_Word
retf
fProc_Set_CfgSpace_Word Endp
Set_CfgSpace_Word Proc Near
push bx
mov bh, CURRENT_BUS_NO[bp]
call ASet_CfgSpace_Word
pop bx
ret
Set_CfgSpace_Word Endp
;-----------------------
;-----------------------
Public fProc_Set_CfgSpace_Dword
fProc_Set_CfgSpace_Dword Proc Far
call Set_CfgSpace_Dword
retf
fProc_Set_CfgSpace_Dword Endp
Set_CfgSpace_Dword Proc Near
push bx
mov bh, CURRENT_BUS_NO[bp]
call ASet_CfgSpace_Dword
pop bx
ret
Set_CfgSpace_Dword Endp
;[]================================================================[]
;[]================================================================[]
ALIGN 4
Public Pci_IO_Mem_Init
Pci_IO_Mem_Init Proc Near
call fProc_Pci_IO_Mem_Init
ret
Pci_IO_Mem_Init Endp
;--------------------------------------------------------------------
;if any shadow segment is not used
; ---> call hook in PCICHIP.ASM to disable it
;
;if any shadow segment is originally not available for PCI ROM
; ---> if setup setting is set to ENABLE
; do nothing
; else
; call hook in PCICHIP.ASM to disable it
;--------------------------------------------------------------------
ALIGN 4
public Disable_UnUsed_Shadow
Disable_UnUsed_Shadow Proc Near
POST_FUNC_CALL EDisable_UnUsed_Shadow
ret
Disable_UnUsed_Shadow Endp
;---------------------------------------------------------------------------
;
; copy ROM image from SI:0 --> DI:0
;
;Input : SI = source segment
; DI = Destination segment
; AL <> 0 : copy size depends on ROM size in SI:2
; == 1 : copy size = input CX (no. of 4K)
;
;---------------------------------------------------------------------------
ALIGN 4
Public Copy_ROM
Copy_ROM Proc Near
POST_FUNC_CALL ECopy_Rom
ret
Copy_ROM Endp
;R82 ;[]============================================================[]
;R82 ;Input : CL = Request Memory spaces with size = CL * 4K
;R82 ; e.g. CL = 1 --> request 4K bytes
;R82 ;
;R82 ;Output : AL = 1 --> NC : AVAIL_LMEM_ADDR[bp] = availbale address
;R82 ; CF : No address available
;R82 ;[]============================================================[]
;R82 ALIGN 4
;R82 ASSUME DS:NOTHING
;R82 Public Get_Available_LMEM
;R82 Get_Available_LMEM Proc Near
;R82
;R82 POST_FUNC_CALL EGet_Available_LMEM
;R82 ret
;R82
;R82 Get_Available_LMEM Endp
;[]============================================================[]
;Enter Protected Mode with DS point to 00000000h
;[]============================================================[]
ALIGN 4
Public Enter_Protect_Mode
Enter_Protect_Mode Proc Near
mov ax, cs
mov ds, ax
assume ds:dgroup
lgdt fword ptr GDTR1
mov eax, cr0
or al, 1
mov cr0, eax
;R47 jmp $+2 ; flush queue
mov ax, DATA1_INDEX
mov ds, ax ; ds = 00000000h
ifndef MP_SUPPORT ;R73A
mov ss, ax ;R73
endif; MP_SUPPORT ;R73A
ret
Enter_Protect_Mode Endp
;[]============================================================[]
;[]============================================================[]
ALIGN 4
Public Leave_Protect_Mode
Leave_Protect_Mode Proc Near
mov eax, cr0
and al, NOT 1
mov cr0, eax
;R47 jmp $+2 ; flush queue
ifndef MP_SUPPORT ;R73A
xor ax, ax ;R73
mov ss, ax ;R73
endif; MP_SUPPORT ;R73A
ret
Leave_Protect_Mode Endp
;[]============================================================[]
;Input : CH - Slot identification Number
;Output : AX - VENDER ID
;Destroy: AX
;[]============================================================[]
Public fProc_Get_Vendor_ID
fProc_Get_Vendor_ID Proc Far
call Get_Vendor_ID
retf
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