cpu586.asm

AWARD BIOS源代码,支持的CHIPSET请看文件,有同型号的板子烧上去就可以跑

; 	[]===========================================================[]
;
;	NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R)
;	        INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE
;	        DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED
;	        WRITTEN AUTHORIZATION FROM THE OWNER.
;
; 	[]===========================================================[]
;
;----------------------------------------------------------------------------
;Rev  	Date	 Name	Description
;----------------------------------------------------------------------------
;R06A	05/10/99 RAY	Since we are using a subtraction algorithm, i.e.
; 			(e.g. 24Mb total memory -->
;       		 AAR7 0-23M cacheable, AAR6 24M-31M non-cacheable)
; 			to calculating the cacheable region of Cyrix MII
;
;			Thus we only have to program the WL bit of RCR7(AAR7)
;
;R07	05/06/99 RCH	Added PRrating table for Rise CPU for clock ratio
;			x2.5 , x3 and x3.5
;R06	04/02/99 MIL	Set bit 2 WL(Weak_Locking) of Cyrix M II CPU internal
;			Region Control Register, for got better performance.
;R05	03/31/99 RCH	Update Cyrix M II CPU Prating table :
;				Frquency     PR from	to
;				---------    -------	---
;				285(95x3)	350	400
;				292(83x3.5)	366	400
;				300(75x4)	366	400
;				300(100x3)	380	433
;				315(90x3.5)	366	433
;				333(83x4)	400	466
;				333(95x3.5)	400	466
;				350(100x3.5)	433	500
;				360(90x4)	433	500
;				380(95x4)	450	533
;				400(100x4)	466	550
;
;R04	03/26/99 MIL	Record Host clock in shadow memory "P6HostClock" for
;			AMD Mode 8 & Cyrix M2 Series CPU.
;R03	03/24/99 RCH	Added 112Mhz host clock support for Pentium class
;			(socket 7) platform. Also fixing wrong CPU clock
;			display for 133Mhz host clock
;R02	03/17/99 RIC	Add "Disable_WT_ALLOC_When_Cyrix_100" for special
;			customer request.
;R01	03/17/99 RCH	Added more CPU models support for Rise. It include
;			052x, 059x for model 5 CPU & 060x,064x for model 6.
;R00	03/15/99 RAY	Initial revision in which the code is extracted from
;			the original CPUPOST.ASM. To prevent compilation error
;			Please define "CPU_586_ONLY" in your BIOS.CFG

IF	COMPILE_FOR_E0
if	STR_function	EQ	1
		extrn	CT_OPEN_SM_RAM:near
		extrn	CT_CLOSE_SM_RAM:near
		extrn	Get_SMBASE_ADD:near
endif	;STR_function	EQ	1

 ifdef	L2ECC_CMOS
		extrn	L2Ecc_Item:near
 endif;	L2ECC_CMOS

		extrn	POST_decompress:near
		extrn	F000_GetItem_Value:near
		extrn	ExtCache_Item:near

		EXTRN	ROM_AND_CMOS:NEAR
		EXTRN	ROM_OR_CMOS:NEAR
		extrn	POST_func_end:Near
		extrn	POST_VECT:Near

		extrn	Check_Cyrix_Cpu:near
		extrn	Init_Cyrix_Reg:near
		extrn	Get_Cmos:near
		extrn	Set_Cmos:near
		extrn	F000_call_proc:near
		extrn	F000_Shadow_W:Near
		extrn	F000_Shadow_R:Near

		extrn	LOCK_CYRIX:Near
		extrn	UNLOCK_CYRIX:Near
		extrn	LOCK_CYRIX:Near
		extrn	SET_CYRIX:Near
		extrn	GET_CYRIX:Near
		extrn	Check_M1_Cpu:near
		extrn	F000_Get_Cmos:near
		extrn	F000_Set_Cmos:near

ifdef	ESCD_SUPPORT
ifndef	ESCD_M2
IF BUS_TYPE NE EISA_BUS
		extrn	P5_BtB_Loc:near
endif; BUS_TYPE NE EISA_BUS
endif;	ESCD_M2
endif;	ESCD_SUPPORT

 		extrn	Check_K586_Cpu:Near
		extrn	Read_CpuID:Near
		extrn	Ct_MemHole_Status:Near
		extrn	Check_M2Cpu:near
		extrn	Check_IdtCpu:Near
		extrn	Check_RiseCpu:Near

		extrn	WinChip2A_Clock_Multiplier_In_AH:far
		extrn	fPROC_If_WinChip2A:Far
		extrn	Cpu_Cache:near

ifdef	Special_CPU_Clock_Table
		extrn	Ct_Int_Clock_Tbl:Near
endif	;Special_CPU_Clock_Table

.LIST

EGROUP		GROUP	ECODE
ECODE		SEGMENT USE16 PARA PUBLIC 'ECODE'
		ASSUME	CS:EGROUP,DS:EGROUP

;=============================================================================
;FUNC:	CYRIX_INIT
;
;DESC:	Handles the initialization of the CYRIX CPU.
;
;IN:	NONE
;OUT:	NONE
;
;SAVES:	NONE + NO STACK
;
;BY:	Richard Chen
;DATE:	18 May 1992
;=============================================================================
FLAGS_MASK	EQU	08D5H

		public	CYRIX_INIT
CYRIX_INIT	proc	near

		F000_call	Init_Cyrix_Reg

		ret

CYRIX_INIT	endp

M2Cpu_Tbl:
		db	21h,23h		;wrong stepping
		dw	CPU_M1_2	;2/1 for M1
M2CPU_LEN	EQU	($ - offset M2Cpu_Tbl)
		db	51h,59h		;2/1 for M2
		dw	CPU_M1_2
		db	52h,5Ah		;2.5/1 for M2
		dw	CPU_M1_3
		db	53h,5Bh		;3/1 for M2
		dw	CPU_M1_3
		db	54h,5Ch		;3.5/1for M2
		dw	CPU_M1_3
		db	55h,5Dh		;4/1 for M2
		dw	CPU_M1_3
		db	0

Check_M2_M1_Cpu	proc	near

;Cyrix have a cut of wrong CPU ID ( 21H & 23H ) . We implement it in boot
;block BOOTROM.ASM , but this 8K code can not be updated if INTEL boot block
;flash was used. So re-check the CPU here.

		F000_call	Check_Cyrix_Cpu
		jnz	Not_Wrong_M1

		;check if M1 already
		mov	al,CMOS_AWARD_2 NMI_OFF	; al = CMOS location
		call	F000_Get_Cmos
		and	al,CPU_TYPE_MASK
		cmp	al,TYPE_M1		;M1 CPU ?
		je	Not_Wrong_M1

		mov	al,0feh			;DIR 0
		out	22h,al
		in	al,23H			;read CPU device ID

		call	Check_M2_Cpu
		jc	Not_Wrong_M1

;set CPU type

		;clear clock mode , SMI bit and WB bit
		mov	al,OVERRIDE NMI_OFF
		call	F000_Get_Cmos
		mov	ah,al
		and	ah,NOT (CLOCK_MODE+((SMICPU+WBCPU) SHR 8))
		or	ah,bh
		mov	al,OVERRIDE NMI_OFF
		call	F000_Set_Cmos

		;set CPU type in CMOS
		mov	ah,bl
		mov	al,CMOS_AWARD_2 NMI_OFF	; al = CMOS location
		call	F000_Set_Cmos
Not_Wrong_M1:
		ret

Check_M2_M1_Cpu	endp

;Input  : AL - Device ID (DIR0) of M1(M2) CPU
;Output : Zero set - It's M2 CPU , and BX return CPU type to store in CMOS
Check_M2_Cpu	proc	near

		mov	si,offset M2Cpu_Tbl
Check_Next_M2:
		cmp	byte ptr cs:[si],0	;last table ?
		je	Not_M2

		cmp	byte ptr cs:[si],al
		je	Get_M2

		cmp	byte ptr cs:[si+1],al
		je	Get_M2

		add	si,M2CPU_LEN
		jmp	Check_Next_M2

Not_M2:
		stc
		ret
Get_M2:
		mov	bx,cs:[si+2]		;get CPU type
		clc

		ret
Check_M2_Cpu	endp

;Input : none
;Output: carry clear - it's double clock
;	 carry set   - it's not double clock
Check_Cyrix_Dclk	proc	near
Check_Cyrix_Dclk	endp

;[]========================================================================[]
;	Set the IBM CPU's Cacheable region: Bit 32-39 of register 1001h
;	according to the extended memory found!
;[]========================================================================[]
		Public	IBMCPU_Cacheable_Size
IBMCPU_Cacheable_Size	Proc	Near

		ret

IBMCPU_Cacheable_Size	Endp

;[]------------------------------------------------------------------------[]
;[]------------------------------------------------------------------------[]
		Public	Chk_Intel_S_CPU
Chk_Intel_S_CPU	Proc	Near

		push	ds
		pushad

	;replace the original int 06h with a temparary
	;one to prevent trap accurs in some CPUs

		xor	eax,eax			;input value = 1
		mov	ds,ax

		push	dword ptr ds:[4*6]	;save int 06h vector
		mov	word ptr ds:[4*6],offset Temp_Int06
		mov	word ptr ds:[4*6+2], 0e000h

		push	ds

		push	cs
		pop	ds

	;issue special OP code: CPUID(00Fh,0A2h)
	;to check if it is a S-series CPU

		db	0Fh,0A2h		;OP code: CPUID

		mov	si,offset Cpu_Vendor_Tbl
Chk_Nxt_Vendor:
		cmp	word ptr [si],-1 	;last of CPU vendor table

		je	Finish_Cpu_ID		;yes,over !

		cmp	ebx,[si+2]		;check 1st identifier string
		jne	Next_Vendor

		cmp	ecx,[si+6]		;check 2nd identifier string
		jne	Next_Vendor

		cmp	edx,[si+10]		;check 3th identifier string
		je	Good_Vendor

Next_Vendor:
		add	si,SIZE_VENDOR_TBL
		jmp	Chk_Nxt_Vendor

Good_Vendor:
		call	Set_SMI_Bit

		mov	si,[si]	 		;get vendor's CPU ID table
	;Now , we got correct identifier of CPU, next step is to get CPU ID
		mov	eax,1			;eax = 1 to read CPU ID
		db	0fh,0A2h		;CPU ID instruction
		and	al,0f0h			;mask stepping bits b3-b0

Chk_Nxt_CpuID:
		cmp	word ptr [si],-1 	;last of CPU ID table

		je	Finish_Cpu_ID
		cmp	ax,[si]			;match CPU ID ?
		je	Save_Cpu_ID		;yes

		add	si,4			;next CPU ID
		jmp	Chk_Nxt_CpuID

CpuIdNotFound:
Save_Cpu_ID:
		call	CheckNoNPentiumCPU	;skip auto-halt for non-
						;Pentium CPUs
		jc	Not_P5

		cmp	word ptr [si+2],CPU_586		;PENTIUM CPU ?
		jne	Not_P5

ifdef	ESCD_SUPPORT
ifndef	ESCD_M2
IF BUS_TYPE NE EISA_BUS
		cmp	al,10H			;skip BTB for 051x
		je	Skip_BtB
		cmp	al,20H			;skip BTB for 052x
		jne	No_Skip_BtB

Skip_BtB:
	;skip BTB control for updating ESCD
		F000_CALL F000_Shadow_W
	;change instruction from "jne" to "jmp"
		mov	ax,0f000H		;code in F-segment
		mov	es,ax
		mov	byte ptr es:[P5_BtB_Loc],0EBH
		F000_CALL F000_Shadow_R

No_Skip_BtB:

endif; BUS_TYPE NE EISA_BUS
endif;	ESCD_M2
endif;	ESCD_SUPPORT

;Disable PENTIUM parity check in TR1 register
                mov     eax,2
                mov     ecx,eax
                xor     edx,edx
                WRMSR

		;disable auto-halt mode by set bit 6 of TR12
		mov	ecx,0eh
		RDMSR
		xor	edx,edx
		mov	eax,40h
		WRMSR
Not_P5:
		mov	dx,[si+2]		;get CPU ID
		call	Set_CPU_Type_Bits
		jmp	Finish_Cpu_ID

Finish_Cpu_ID:

		pop	ds

		pop	dword ptr ds:[4*6]	;restore int 06h vector

		call	Check_M2_M1_Cpu

		call	Prepare_CPU_Info
		popad
		pop	ds
		ret

;-------------------------------------------------------
; Temporary Int 06 handler for Non-(Intel S-Series) CPU
;-------------------------------------------------------
		public	Temp_Int06

Temp_Int06	Label	Near
		push	bp
		mov	bp,sp
		add	word ptr ss:[bp+2],2
		pop	bp
		iret

Chk_Intel_S_CPU	Endp

;Function : Return Non-Pentium CPU flag
;Input    : carry clear - Pentium CPU
;Output   : carry set   - non-Pentium CPU
CheckNoNPentiumCPU	proc	near
 		pushad

 		xor	eax,eax			;get vendor ID string
 		db	0Fh,0A2h		;OP code: CPUID

	;Check if IDT/C6 CPU
 		cmp	ebx,746e6543h		;C6 vendor ID string match ?
		je	NotIntelP5	;IDT/C6 CPU

	;Check if Rise/mP6 CPU
		cmp	ebx,65736952h		;Rise CPU ?
		jne	OtherNonIntelP5	;no

	;Configuration setup of mP6 CPU family
		mov	eax, 6363452AH
		mov	ecx, 3231206CH
		mov	edx, 2A32313AH
 		db	0Fh,0A2h		;OP code: CPUID

		mov	eax, 63634523H
		mov	ecx, 32315F6CH
		mov	edx, 2333313AH
 		db	0Fh,0A2h		;OP code: CPUID

		jmp	NotIntelP5

OtherNonIntelP5:

		clc				;Intel Pentium CPU
		jmp	NoNPentiumExit
NotIntelP5:
		stc				;for Non-Intel CPUs

NoNPentiumExit:

 		popad
		ret
CheckNoNPentiumCPU	endp

Cpu_Vendor_Tbl:
		dw	offset Cpu_INTELs  	;table of INTEL CPUs
		dd	756E6547h	   	;Identifer string 1
		dd	6C65746eh	   	;Identifer string 2
		dd	49656E69h	   	;Identifer string 3
SIZE_VENDOR_TBL	EQU	$ - offset Cpu_Vendor_Tbl

		dw	offset Cpu_AMDs	   	;table of AMD CPUs
		dd	68747541h	   	;Identifer string 1
		dd	444d4163h	   	;Identifer string 2
		dd	69746e65h	   	;Identifer string 3

		dw	offset Cpu_IDTs		;table of IDT CPUs
		dd	746e6543h		;Identifer string 1
		dd	736c7561h		;Identifer string 2
		dd	48727561h		;Identifer string 3

		dw	offset Cpu_Rise		;table of Rise CPUs
		dd	65736952h		;Identifer string 1(Rise)
		dd	65736952h		;Identifer string 2(Rise)
		dd	65736952h		;Identifer string 3(Rise)

		dw	-1		   	;last of CPU venders table

;CPU table for INTEL s-series CPUs
Cpu_INTELs:

		dw	0510h,CPU_586			;PENTIUM 1/1
		dw	0520h,CPU_586			;PENTIUM 3/2
		dw	2520h,CPU_586			;PENTIUM 2/1
		dw	0540h,CPU_586			;PENTIUM 2/1
		dw	2540h,CPU_586			;PENTIUM 2/1
		dw	1520h,CPU_586			;PENTIUM 2/1 ODP
		dw	1540h,CPU_586			;PENTIUM 2/1 ODP
		dw	0570h,CPU_586			;PENTIUM 3/2
		dw	0580h,CPU_586			;PENTIUM/MMX

		dw	-1				;last of table

		ALIGN	16

;CPU table for AMD s-series CPUs
Cpu_AMDs:

		dw	0500H,CPU_AMD5K86
		dw	0510H,CPU_AMD5K86
		dw	0520H,CPU_AMD5K86
		dw	0530H,CPU_AMD5K86
		dw	0560H,CPU_AMD5K86
		dw	0570H,CPU_AMD5K86
		dw	0580H,CPU_AMD5K86
		dw	0590H,CPU_AMD5K86

		dw	-1

;CPU table for UMC s-series CPUs
Cpu_UMCs:
		dw	-1

Cpu_IDTs:	;table of IDT CPUs
		dw	0520h,CPU_586			;C6 w/o MMX
		dw	0540h,CPU_586			;C6 w/  MMX
		dw	0580h,CPU_586			;WinChip 2
		dw	0590h,CPU_586			;WinChip 2
		dw	-1

;CPU table for Rise s-series CPUs
Cpu_Rise:
		dw	0500h,CPU_586			;mP6
		dw	0510h,CPU_586			;mP6 future
		dw	0580h,CPU_586			;mp6-2 CPU
		dw	0520h,CPU_586			;Rise model 5;R01
		dw	0590h,CPU_586			;Rise model 5;R01
		dw	0600h,CPU_586			;Rise model 6;R01
		dw	0640h,CPU_586			;Rise model 6;R01
		dw	-1				;last of table

;[]==========================================================[]
;[]==========================================================[]
		Public	Chk_If_Type_P24C
Chk_If_Type_P24C:
		ret

;[]==========================================================[]
;[]==========================================================[]
		Public	Set_SMI_Bit
Set_SMI_Bit:
		mov	ah,CMOS_OVERRIDE NMI_OFF
		mov	al,ah

		call	F000_Get_Cmos
		or	al,SMICPU shr 8
		xchg	ah,al

		call	F000_Set_Cmos
		ret

;[]==========================================================[]
;[]==========================================================[]
		Public	Clear_SMI_Bit
Clear_SMI_Bit:
		mov	ah,CMOS_OVERRIDE NMI_OFF
		mov	al,ah

		call	F000_Get_Cmos
		and	al,NOT (SMICPU shr 8)
		xchg	ah,al

		call	F000_Set_Cmos
		ret

;[]==========================================================[]
;[]==========================================================[]
		Public	Chk_SMICPU_Bit
Chk_SMICPU_Bit:
		push	ax
		mov	al,CMOS_OVERRIDE NMI_OFF