pmupost.asm

AWARD BIOS源代码,支持的CHIPSET请看文件,有同型号的板子烧上去就可以跑

;===============================================================
endif	;NEW_SUPERVGA_KERNEL
;R56 - ends

;---------------------------------------------------------------------------
;R49 - starts
ifdef	Notebook_Power_Management
		Public	F_Suspend_0V
F_Suspend_0V	proc	Far
		call  Suspend_0V
		ret
F_Suspend_0V	ENDP
F_Resume_0V	Proc	Far
 		Call Resume_0V
 		ret
F_Resume_0V	Endp
endif	;Notebook_Power_Management
;R49 - ends

FCODE		ENDS

;--------------------------------------------------------------
;--------------------------------------------------------------
;----- The following codes will be located at E000 ! ----------
;----- The following codes will be located at E000 ! ----------
;----- The following codes will be located at E000 ! ----------
;----- The following codes will be located at E000 ! ----------
;--------------------------------------------------------------
;--------------------------------------------------------------
EGROUP		GROUP	ECODE
ECODE		SEGMENT USE16 PARA PUBLIC 'ECODE'
		ASSUME	CS:EGROUP,DS:G_RAM,ES:EGROUP
		align	4


if	STD_Function	EQ	1

;[]========================================================================[]
;
;Procedure:	CT_0V_Shutdown
;
;Function :	Routine to put system into off state.
;
;Input	  :	None
;
;Output   :	None
;
;[]========================================================================[]
		Public	CT_0V_Shutdown	
CT_0V_Shutdown	Proc	Near
		mov	ax,PM_RAM_SEGMENT
		mov	ds,ax
		extrn	APM_16_PowerOff:near
		F000_call	DGROUP:APM_16_PowerOff
		ret
CT_0V_Shutdown	Endp

;[]========================================================================[]
;
;Procedure:	CT_System_Wakeup
;
;Function :	Routine for system wake up from Zero-Volt-Suspend.
;
;Input	  :	None
;
;Output   :	None
;
;[]========================================================================[]
		Public	CT_System_Wakeup
CT_System_Wakeup	Proc	Near
		ret
CT_System_Wakeup	Endp

;[]========================================================================[]
;
; Suspend_Chipset_Table
;
;	This table describe chipset registers which save & restore during
;	Zero-Volt-Suspend & Resume.
;	It is refrenced by routine Save_Chipset & Restore_Chipset.
;
;	Formate:
;
;		DW	<Register Index start>, <Regisetr counts>
;		DW		:			:
;		DW		:			:
;		DW		:			:
;		DW	<Register Index start>, <Regisetr counts>
;		DW	FFFFh					; End of table
;
;
;[]========================================================================[]
		PUBLIC	Suspend_Chipset_Table
Suspend_Chipset_Table:
;R49C;R49B		dw	VT586 + 00h,     	100h
;R49C 		dw	VT586 + 00h,     	37h	;R49B
;R49C 		dw	VT586 + 47h,     	60h	;R49B
;R49C 		dw	VT586_IDE + 00h,	100h
;R49C 		dw	VT586_USB + 00h,	100h
;R49C 
;R49C		dw	VT586_ACPI + 00h,	14h	   ;R49B
;R49C 		dw	VT586_ACPI + 16h,	40h - 16h  ;R49B
;R49C ifdef	VT686
;R49C  		dw	VT586_USB_2 + 10h,	31h
;R49C  		dw	VT686_AC97 + 10h,	30h
;R49C  		dw	VT686_AC97 +100h+10h,	30h	;MC97 function 6 
;R49C endif;	VT686

;R49		dw	VT586_ACPI + 00h,	14h
;R49		dw	VT586_ACPI + 16h,	40h - 16h
;R49A		dw	VT586_ACPI + 40h,	1;R49

;R49C - starts
		dw	VT692 + 10h,     	90h
		dw	VT692_PP + 10h,     	30h

 		dw	VT586 + 00h,     	37h
 		dw	VT586 + 47h,     	60h
 		dw	VT586_IDE + 00h,	100h
 		dw	VT586_USB + 00h,	100h
 
 		dw	VT586_ACPI + 16h,	40h - 16h
;R49C - ends
		dw	0FFFFh

;[]========================================================================[]
;Procedure:	Get_SMBASE_Seg
;
;Function :	Return SMBASE segment.
;
;Input	  :	None
;
;Output   :	EAX: should point to the SMBASE address (32bit address).
;
;[]========================================================================[]
		Public	Get_SMBASE_SEG
Get_SMBASE_SEG	Proc	Near
		mov	eax, 0A0000h
		ret
Get_SMBASE_SEG	Endp

;[]========================================================================[]
;Procedure:	CT_AllShadow_RW
;
;Function :	To Enable/Disable all shadow Read/Write.
;
;Input	  :	AL = 0 For all shadow readable.
;		AL = 1 For all shadow writeable.
;
;Output   :	None
;
;Preserve :
;
;Note	  :	1. Stack available.
;		2. called from Suspend_0V or Resume_0V.
;		3. If the chipset support shadow RAM both Readable & Writeable
;		   then don't care input AL, Just program chipset for shadow
;		   RAM both R/W-able.
;
;[]========================================================================[]
		Public	CT_AllShadow_RW
CT_AllShadow_RW	Proc	Near
		pusha
		push	ebx
		mov	cx,VT692 + 61h
		mov	bl,0FFh
		call	E000_GET_SET_PMU_OR
		inc	cl
		call	E000_GET_SET_PMU_OR
		inc	cl
		mov	bl,0F0h
		call	E000_GET_SET_PMU_OR
		pop	ebx
		popa
		ret
CT_AllShadow_RW	Endp

;[]========================================================================[]
;Procedure:	CT_SMBASE_Off
;
;Function :	To disable SMBASE map function.
;
;Input	  :	None
;
;Output   :	None
;
;[]========================================================================[]
		Public	CT_SMBASE_Off
CT_SMBASE_Off	Proc	Near
		pusha	   
		push	ebx
		mov	cx,VT692+63h
;R44		mov	bx,00Fch
		mov	bx,02Fch	;R44
		call	E000_GET_SET_PMU
		pop	ebx
		popa
		ret
CT_SMBASE_Off	endp

;[]========================================================================[]
;Procedure:	CT_SMBASE_On
;
;Function :	To Enable SMBASE map function.
;
;Input	  :	None
;
;Output   :	None
;
;[]========================================================================[]
		Public	CT_SMBASE_On
CT_SMBASE_On	Proc	Near
		pusha
		push	ebx
		mov	cx,VT692+63h
		mov	bx,00FCh	;R49A
;R49A		mov	bx,03FCh
		call	E000_GET_SET_PMU
		pop	ebx
		popa
		ret
CT_SMBASE_On	Endp

;[]========================================================================[]
;Procedure:	CT_Disable_SMI
;
;Function :	To disable SMI trigger.
;
;Input	  :	None
;
;Output   :	None
;
;[]========================================================================[]
		Public	CT_Disable_SMI
CT_Disable_SMI	Proc	Near
		ret
CT_Disable_SMI	Endp
;[]========================================================================[]
;Procedure:	CT_Skip_ZV_Shadow
;
;Function :	To tell ZV suspend kernal that do not save/restore shadow RAM
;		if it is need.
;
;Input	  :	AX = shadow RAM segment C000H,D000H,E000H,F000H.
;
;Output   :	ZF = Skip this segment save/restore during ZV susupend/resume.
;		NZF = This segment save/restore during ZV susupend/resume.
;
;Save	  :	AX
;
;Note	  :	Sometime chipset use shadow RAM for SMBASE, So it is need to
;		skip shadow RAM save/restore during ZV susupend/resume.
;		Refrence the chipset Sis-550X for this case.
;
;[]========================================================================[]
		Public	CT_Skip_ZV_Shadow
CT_Skip_ZV_Shadow	Proc	Near
		or	ax,ax
		ret
CT_Skip_ZV_Shadow	Endp

		Public	Save_Ct_device
Save_Ct_device	Proc	near
		ret
Save_Ct_device	Endp

		Public	Restore_Ct_device
Restore_Ct_device	Proc	Near
		ret
Restore_Ct_device	Endp

ifdef	S4_Support
		Public	Wakeup_Device
Wakeup_Device	Proc	NEAR

	; Enable IDE Channel
		push	ebx
		mov	cx, VT586_IDE+04H
		mov	bl, 05h
		Call	E000_Get_Set_PMU_OR
		pop	ebx
		ret

Wakeup_Device	Endp
endif;	S4_Support
endif	;STD_Function

ifdef	ACPI_Support
;[]========================================================================[]
;Procedure:	Ct_ACPI_Option
;
;Function :	Return ACPI on/off status
;
;Input	  :	None
;
;Output   :	CF = 1   ACPI off
;		CF = 0   ACPI on
;[]========================================================================[]
		Public	Ct_ACPI_Option
Ct_ACPI_Option	Proc	Near


;R26  IFNDEF	No_ACPI_IRQ_Selectable
  IFDEF	ACPI_IRQ_Selectable			;R26
		mov	si,offset Assign_ACPI_IRQ_Item
		call    F000_GetItem_Value
		or	al,al			; if ACPI IRQ set NA ?
		jnz	short @F		; No, jmp !
		stc				; Set Not ACPI
		ret
@@:
;R26  ENDIF;	No_ACPI_IRQ_Selectable
  ENDIF;ACPI_IRQ_Selectable			;R26

		mov	si,offset ACPI_option_Item
                call    F000_GetItem_Value
		or	al,al			;Enable ACPI ?
		clc				; Set Is ACPI
		jz	short @F		;Yes
		stc				; Set Not ACPI
@@:
		ret

Ct_ACPI_Option	Endp
endif;	ACPI_Support

;[]========================================================================[]
;Procedure:	E000_Ct_Early_PM_Init
;
;Function :	Early PM chip initializations
;
;Input	  :	None
;
;Output   :	None
;
;Preserve :	All
;
;Note	  :	1. Call from POST 9
;		2. Stack available
;		3. You can initialize any PM function which is needed
;		   to be done earlier!
;[]========================================================================[]
		Public	E000_Ct_Early_PM_Init
E000_Ct_Early_PM_Init	Proc	Near

		push	ds
		push	es
		pushad
		cld
ifdef	Wake_On_GPI_Support			;R14 - starts
		mov	al,55h NMI_OFF			; CMOS [55h] :
		out	70h,al			; bit 4 :  Wake_On_GPI_Support
		in	al,71h			;
		and	al,10h
		shr	al,4
		shl	al,Wake_On_GPI_Support
		mov	bh, al
		mov	cl, 24h			;
		mov	bl, not (01h shl Wake_On_GPI_Support)
		call	E000_Get_Set_PMIO	;
endif;	Wake_On_GPI_Support			;R14 - ends

ifdef	VT596
		mov	bl,not 04h		;R27 Set RTC Alarm Resume Off
		mov	cl, 03h			;R27
		call	E000_Get_Set_PMIO_AND	;R27

		mov	dx,ACPI_Port + 00h	
		in	ax,dx	       		
		out	dx,ax			
		mov	dx,ACPI_Port + 20h	;R06
		in	ax,dx	       		;R06
		out	dx,ax			;R06
		mov	dx,ACPI_Port + 30h	;R06
		in	ax,dx	       		;R06
		out	dx,ax			;R06
		mov	dx,ACPI_Port + 32h	;R06
		in	ax,dx	       		;R06
		out	dx,ax			;R06
		mov	dx,ACPI_Port + 28h	;R04
		in	ax,dx	       		;R04
		out	dx,ax			;R04
  IFNDEF	Power_Button_Dont_Set_Level_Trigger	;R16 - starts
		mov	cl, 2Ch			; Set Power Button to
		mov	bl, 04h			;	Level Trigger
		call	E000_Get_Set_PMIO_OR	;
  ENDIF;	Power_Button_Dont_Set_Level_Trigger	;R16 - ends
  IFDEF	Always_Enable_LID			;R18 - starts
		mov	cl, 25h			; Always Enable LID#
;R18A		mov	bl,80h			;
		mov	bl,08h			;R18A
		call	E000_Get_Set_PMIO_OR	;
  ENDIF;Always_Enable_LID			;
  IFDEF	WAKE_LAN_BY_LID
		mov	al,55h NMI_OFF			; CMOS [55h] :
		out	70h,al			; bit 4 :  WAKE_LAN_BY_LID
		in	al,71h			;
		and	al,10h
		shr	al,1
		mov	bh, al
		mov	bl, not 08h
		mov	cl, 25h			; 25h bit 3 : LID#
		call	E000_Get_Set_PMIO	;

    ifdef	WAKE_LAN_BY_GPI			;R61
		shr	bh, 3			;R61
		mov	cl, WAKE_LAN_BY_GPI 	;R61
		shl	bh, cl			;R61
		mov	bl, bh			;R61
		not	bl			;R61
		mov	dx, ACPI_Port + 24h	;R61
		in	al, dx			;R61
		and	al, bl			;R61
		or	al, bh			;R61	
		mov	dx, ACPI_Port + 24h	;R61
		out	dx, al			;R61
    endif;	WAKE_LAN_BY_GPI			;R61

   IFDEF	LID_ACTIVE_HIGH			;R30A - starts
		mov	cl, 2Ch			; 2Ch bit 7 : LID# Rising Trigger
		mov	bl,not 80h		;
		call	E000_Get_Set_PMIO_AND	;
   ELSE;	LID_ACTIVE_HIGH			;R30A - ends
    ifndef	LID_Triger_By_Rising_Edge	;R30
		mov	cl, 2Ch			;R30 2Ch bit 7 : LID# Falling Trigger
		mov	bl, 80h			;R30
		call	E000_Get_Set_PMIO_OR	;R30
    else;	LID_Triger_By_Rising_Edge	;R30A
		mov	cl, 2Ch			;R30A 2Ch bit 7 : LID# Rising Trigger
		mov	bl,not 80h		;R30A
		call	E000_Get_Set_PMIO_AND	;R30A
    endif;	LID_Triger_By_Rising_Edge	;R30
   ENDIF;	LID_ACTIVE_HIGH			;R30A

  ENDIF;WAKE_LAN_BY_LID				;R18 - ends
endif;	VT596

                mov     ax,cs
                mov     ds,ax
                mov     ax,03800h               ; orginal CPU SMBase
                mov     es,ax
                mov     cx,Change_SMBase_L      ;dword length
                mov     si,offset Change_SMBase
                xor     di,di
                rep     movsb

; Enable SMI
		Call	E000_Ct_Enable_SMI

                F000_call       Issue_SW_SMI    ;Change SMBASE
		xor	cx, cx			
@@:						
		loop	@B			
;R11 M1_Cpu:


; Disable all SMI

; Enable SMI
; **** Change_SMBase subroutine is executing at this point in SMM Mode ****
; **** After this poin