📄 chippost.asm
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call far ptr X_Cache_Init ;Docket is PCI IRQ initialize
;R48 - start
ifdef MP_SUPPORT
extrn Cpu_Apic_Init:near
call Cpu_Apic_Init
endif; MP_SUPPORT
;R48 - end
clc
ret
Cache_Init endp
;[]==============================================================[]
;Ct_Parity_Control: (POST 52h)
; Programming chipset registers of memory parity check
;Saves: all but flags
;Input: AL - 0 = disable parity check
; - 1 = enable parity check
;Output:none
;
;[Notes] 1. Stack and BP is available
; 2. This function can be used to program special chipset
; registers about memory parity check
;[]==============================================================[]
public Ct_Parity_Control
Ct_Parity_Control proc near
ret ; Dummy Return
Ct_Parity_Control endp
;[]==============================================================[]
;CT_FINAL_INIT: (POST 61h)
; Programming chipset registers before boot
;Saves: all but flags
;Input: none
;Output:none
;
;[Notes] 1. Stack and BP is available
; 2. This function can be used to program special chipset
; registers before boot
;[]==============================================================[]
public CT_FINAL_INIT
CT_FINAL_INIT proc near
call far ptr X_ct_final_init
ret
CT_FINAL_INIT endp
;[]==============================================================[]
;Get_Cache_Size: (POST 61h)
; Return chipset cache size to display
;Input : None
;Output: AL - 0 = 0K, 1=16K , 2=32K , 3=64K , 4=128K , 5=256K
; 6 =512K, 7=1024K ,etc...
;[]==============================================================[]
PUBLIC Get_Cache_Size
Get_Cache_Size PROC NEAR
ret ; Dummy Return
Get_Cache_Size ENDP
;[]==============================================================[]
;GET_CPU_SPEED: (POST 0Dh)
; Program some chipset registers according to CPU clock
; in G_RAM:CPU_CLOCK
;Saves: all but flags
;Input: none
;Output:none
;
;[Notes] 1. Stack and BP is available
; 2. You can program AT bus clock to about 8Mhz according
; to cpu clock
;[]==============================================================[]
PUBLIC Get_CPU_Speed
Get_Cpu_Speed proc near
ret ; Dummy Return
Get_Cpu_Speed endp
;[]==============================================================[]
;CT_REMAP: (POST 30h)
; Remap unused memory from 640k to 1M
;Saves: all but flags
;Input: none
;Output:none
;[Notes] 1. Program chipset register if remap allowed.
;[]==============================================================[]
public Ct_Remap
Ct_Remap proc near
call far ptr E000_Ct_Remap
;R07A ;R07 - starts
;R07A ifdef CAS_Latency_Error_String
;R07A call far ptr X_CAS_Latency_Error_String
;R07A endif; CAS_Latency_Error_String
;R07A ;R07 - ends
ret
Ct_Remap endp
;[]==============================================================[]
;Ct_Disable_Onboard_Vga: (Reserved)
; Disable onboard C000H video ROM by setting chipset register
; Input : None
; Output: None
; Save: all
; [Note]: 1. This is used to auto-detect onboard C0000H video ROM
; and video ROM on slot.
;[]==============================================================[]
public Ct_Disable_Onboard_Vga
Ct_Disable_Onboard_Vga proc near
ret
Ct_Disable_Onboard_Vga endp
;[]==============================================================[]
;Ct_Enable_Onboard_Vga (Reserved)
; Enable onboard C000H video ROM by setting chipset register
; Input : None
; Output: None
; Save: all
; [Note]: 1. This is used to auto-detect onboard C0000H video ROM
; and video ROM on slot.
;[]==============================================================[]
public Ct_Enable_Onboard_Vga
Ct_Enable_Onboard_Vga proc near
ret
Ct_Enable_Onboard_Vga endp
;[]==============================================================[]
;Ct_Disable_E000_Vga: (Reserved)
; Disable onboard E000H video ROM by setting chipset register
; Input : None
; Output: None
; Save: all
; [Note]: 1. This is used to auto-detect onboard E0000H video ROM
; and video ROM on slot.
;[]==============================================================[]
public Ct_Disable_E000_Vga
Ct_Disable_E000_Vga proc near
ret
Ct_Disable_E000_Vga endp
;[]==============================================================[]
;Ct_Enable_E000_Vga: (Reserved)
; Enable onboard E000H video ROM by setting chipset register
; Input : None
; Output: None
; Save: all
; [Note]: 1. This is used to auto-detect onboard E0000H video ROM
; and video ROM on slot.
;[]==============================================================[]
public Ct_Enable_E000_Vga
Ct_Enable_E000_Vga proc near
ret
Ct_Enable_E000_Vga endp
;[]==============================================================[]
;Ct_Check_System_Shadow: (Reserved)
; Check sytem BIOS is shadowed or not.
; Input : None
; Output: flag zero set - System BIOS is shadowed
; zero clear - System BIOS is not shadowed
; Save: all except ax
; [Note]: 1. This is used to fix NOVELL problem on user-defined
; hard disk.
; 2. You must return real status of system shadow,
; otherwise may boot fail on HDD.
;[]==============================================================[]
public Ct_Check_System_Shadow
Ct_Check_System_Shadow proc near
ret
Ct_Check_System_Shadow endp
;[]==============================================================[]
; Ct_Init_Cyrix : (POST 09h) (CPUPOST.asm INIT_CYRIX )
; Program chipset register for CYRIX CPU
; Input : None
; Output: None
; Save: all
; [Note]: 1. Just return if chipset did not need programming
;[]==============================================================[]
public Ct_Init_Cyrix
Ct_Init_Cyrix proc near
ret ; Dummy Return
Ct_Init_Cyrix endp
;R21;[]==============================================================[]
;R21; Disable_E000_ROM_Shadow : (POST 63h)
;R21; Disable E000 ROM Shadow (Direct Access to ISA)
;R21; Input : None
;R21; Output: None
;R21; Save: all
;R21;[]==============================================================[]
;R21 public Disable_E000_ROM_Shadow
;R21Disable_E000_ROM_Shadow proc near
;R21
;R21 ;disable E0000 shadow RAM
;R21
;R21 mov cx,VT692 + 63h
;R21 mov bl,NOT 0c0H
;R21 call Get_Set_Ct_AND
;R21
;R21 ;disable onboard E0000 ROM
;R21 mov cx,VT586 + 43h
;R21 mov bl,NOT 30H
;R21 call Get_Set_Ct_AND
;R21
;R21 ret
;R21Disable_E000_ROM_Shadow endp
;[]==============================================================[]
;Check C0000-EFFFF shadow allowed or not (POST 0Eh)
; Some chipset's shadow is dependent on F0000 shadowing, i.e.
; If F0000 was not shadowed, all other segment of ROM can't be
; shadowed.
;Input : none
;Output: zero set - shadow allow
; zero not set - shdow not allow
;[]==============================================================[]
public Ct_Shadow_Alone_Check
Ct_Shadow_Alone_Check proc near
ifndef No_SDRAM_Load_Default ;R12 - starts
IFDEF Clear_SDRAM_Load_D4_In_POST0E
;-----------------------------------------------;
; Reset the Status of SDRAM_Load_Default ;
;-----------------------------------------------;
IFNDEF SDRAM_Load_Default_CMOS
mov al, [bp]+ 37h
and al, not (03h)
or al, ((03h shl 1) and (03h))
mov [bp]+37h, al
ELSE; SDRAM_Load_Default_CMOS
mov al, [bp]+ SDRAM_Load_Default_CMOS
and al, not (SDRAM_Load_Default_Bit)
or al, ((SDRAM_Load_Default_Bit shl 1) and (SDRAM_Load_Default_Bit))
mov [bp]+SDRAM_Load_Default_CMOS, al
ENDIF; SDRAM_Load_Default_CMOS
ENDIF;Clear_SDRAM_Load_D4_In_POST0E
endif ;No_SDRAM_Load_Default ;R12 - ends
xor al,al
ret
Ct_Shadow_Alone_Check endp
;[]==============================================================[]
;C000_Shadow_RW:
; Set video BIOS(C000-C800) shadow enable & writeable
;Input : none
;Output: none
;[]==============================================================[]
public C000_Shadow_RW
C000_Shadow_RW proc near
mov cx,VT692 + 61h
mov bx,0ff0h
call GET_SET_CT
ret
C000_Shadow_RW endp
;[]==============================================================[]
;C000_Shadow_R:
; Set video BIOS(C000-C800) shadow readonly
;Input : none
;Output: none
;[]==============================================================[]
public C000_Shadow_R
C000_Shadow_R proc near
mov cx,VT692 + 61h
mov bx,0af0h
call GET_SET_CT
ret
C000_Shadow_R endp
;[]==============================================================[]
;E000_Shadow_W:
; Set video BIOS(E000-E800) shadow enable & writeable
;Input : none
;Output: none
;[]==============================================================[]
public E000_Shadow_W
E000_Shadow_W proc near
mov cx,VT692 + 63h
mov bx,403fh
call GET_SET_CT
ret
E000_Shadow_W endp
;R21;[]==============================================================[]
;R21;E000_Shadow_R:
;R21; Set video BIOS(E000-E800) shadow readonly
;R21;Input : none
;R21;Output: none
;R21;[]==============================================================[]
;R21 public E000_Shadow_R
;R21E000_Shadow_R proc near
;R21 mov cx,VT692 + 63h
;R21 mov bx,803fh
;R21 call GET_SET_CT
;R21 ret
;R21E000_Shadow_R endp
;[]==============================================================[]
;C800_Shadow: (Reserve)
; Shadow adaptor ROM C8000-CBFFF
;CC00_Shadow: (Reserve)
; Shadow adaptor ROM CC000-CFFFF
;D000_Shadow: (Reserve)
; Shadow adaptor ROM D0000-D3FFF
;D400_Shadow: (Reserve)
; Shadow adaptor ROM D4000-D7FFF
;D800_Shadow: (Reserve)
; Shadow adaptor ROM D8000-DBFFF
;DC00_Shadow: (Reserve)
; Shadow adaptor ROM DC000-DFFFF
;E000_Shadow: (Reserve)
; Shadow adaptor ROM E0000-E3FFF
;E400_Shadow: (Reserve)
; Shadow adaptor ROM E4000-E7FFF
;E800_Shadow: (Reserve)
; Shadow adaptor ROM E8000-EBFFF
;EC00_Shadow: (Reserve)
; Shadow adaptor ROM EC000-EFFFF
;Input : none
;Output: none
;[]==============================================================[]
public C800_Shadow
public CC00_Shadow
public D000_Shadow
public D400_Shadow
public D800_Shadow
public DC00_Shadow
public E000_Shadow
public E400_Shadow
public E800_Shadow
public EC00_Shadow
C800_Shadow proc near
CC00_Shadow:
D000_Shadow:
D400_Shadow:
D800_Shadow:
DC00_Shadow:
E000_Shadow:
E400_Shadow:
E800_Shadow:
EC00_Shadow:
ret
C800_Shadow endp
Public E000_64K_shadow_RW
E000_64K_shadow_RW Proc Near
mov cx,VT692 + 63h
mov bx,0C03fh
call GET_SET_CT
ret
E000_64K_shadow_RW Endp
;R21 Public E000_64K_shadow_R
;R21E000_64K_shadow_R Proc Near
;R21 jmp E000_Shadow_R
;R21E000_64K_shadow_R Endp
;[]==============================================================[]
;Set_High_Speed: (POST 0Dh)
; Set system to high speed before CPU clock detecting
; during POST
;Input : none
;Output: none
;[]==============================================================[]
Public Set_High_Speed
Set_High_Speed Proc Near
;R26 - start
ifdef HALT_IF_VGA_NOT_FOUND
call far ptr Halt_System_IF_NOVGA
endif; HALT_IF_VGA_NOT_FOUND
;R26 - end
ret
Set_High_Speed Endp
;[]==============================================================[]
;Restore_Speed: (POST 0Dh)
; Restore system speed after CPU clock detecting set by
; Set_High_Speed routine during POST if needed
;Input : none
;Output: none
;[]==============================================================[]
Public Restore_Speed
Restore_Speed Proc Near
ret
Restore_Speed Endp
;[]==============================================================[]
;Init_Onboard_Io: (POST 32h)
; Initial onboard I/O chip
;Save : all but flags
;Input : none
;Output: none
;Note : 1. This routine will be called before I/O installation.
; 2. This is a customerization routine if you need.
;[]==============================================================[]
public Init_Onboard_Io
Init_Onboard_Io proc near
call far ptr X_Init_Onboard_Io
;R07A - starts
IFDEF SMBus_Port ;R46
ifndef No_Suggested_SDRAM_CL
call far ptr X_CAS_Latency_Error_String
endif; No_Suggested_SDRAM_CL
ifndef No_Suggested_DRAM_Clock ;R46
call far ptr X_DRAM_Clock_Error_String ;R46
endif; No_Suggested_DRAM_Clock ;R46
ENDIF; SMBus_Port ;R46
;R07A - ends
ret
Init_Onboard_Io endp
;[]==============================================================[]
;Ct_Before_Setup: (Before SETUP)
; Program some improper registers if problem occured when
; entering setup
;Save : all but flags
;Input : none
;Output: none
;Note : 1. This routine will be called before entering setup
; 2. Some chipset will hang or improper operation while
; entering setup.
;[]==============================================================[]
public Ct_Before_Setup
Ct_Before_Setup proc near
ifdef Record_PWRON_Status
IFDEF PowerFail_As_PIIX4 ;R40
;R32 mov al,0F0h ; Save Flag of Entry SETUP.
mov al,0F4h ;R32 Save Flag of Entry SETUP.
out 72h,al ;
mov al,0A5h ;
out 73h,al ;
ENDIF;PowerFail_As_PIIX4 ;R40
endif; Record_PWRON_Status
ret
Ct_Before_Setup endp
;[]==============================================================[]
;Ct_Auto_Check: (POST 41h)
; Check if program chipset registers with AUTO table or not
;Save : all but flags
;Input : none
;Output: zero flag set - No auto-config.
; zero flag clear - Program with AUTO table
;Note : 1. This routine will be called before auto-programming
; 2. You must read setup value (according setup item )
; to judge auto-programming is allowed or not. and return
; correct zero flag.
;[]==============================================================[]
public Ct_Auto_Check
Ct_Auto_Check proc near
or al,1 ; Clear zero flag
ret
Ct_Auto_Check endp
;[]==============================================================[]
;Ct_Shadow_Allow: (Reserved)
; Check if any shadow RAM available
;Save : all but flags
;Input : none
;Output: zero flag set - shadow RAM available
; zero flag clear - No shadow RAM
;Note : 1. This routine will be called before shadowing
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