chippost.asm

AWARD BIOS源代码,支持的CHIPSET请看文件,有同型号的板子烧上去就可以跑

;	[]===========================================================[]
;
;	NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R)
;		INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE
;		DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED
;		WRITTEN AUTHORIZATION FROM THE OWNER.
;
; 	[]===========================================================[]
;
;----------------------------------------------------------------------------
;Rev    Date     Name   Description
;----------------------------------------------------------------------------
;R51	05/02/99 ADS	Add "GPO_LOW_IF_VIDEO_OK" and "GPO_LOW_IF_MEMORY_OK"
;			option for customer requset.
;R50	04/29/99 RIC	Add "X_If_693A"	routine and
;			public "X_Measure_SDRAM_Speed" routine.
;R49	04/23/99 RAX	Added code to patch 3COM Lan card can't enter low power
;			state and under Win98 APM mode can't work when reset on
;			"even" times.
;R47B	04/22/99 RIC	"VIA_Y2K_Patch" definition can be used in 596B chip.
;R18A	04/20/99 ADS	Fix that the IRQ of SCI assign fail in 
;			new VIA Super SouthBridge VT686.
;R47A	04/08/99 RIC	Add "VIA_Y2K_Patch" definition for R47 code for
;			temporal because it function have some problem.
;R48A	04/08/99 RCH	Support external IOAPIC for MP platform
;R48	04/02/99 RCH	Added support for Multi-Processor platform
;R47	04/01/99 RIC	Add Patch Y2K CMOS 32h function.
;R46A	03/30/99 RIC	Fixed that compile error in "No_Suggested_SDRAM_CL"
;			definition
;R14A	03/25/99 RIC	Fixed that compile error in no "SMBus_Port" definition.
;R46	03/24/99 RIC	Add show DRAM_Clock_Error_String function
;			and "No_Suggested_DRAM_Clock" definition.
;R45	03/16/99 RIC	Fixed that Resume Item auto-hide fail in 596/686A chip.
;R44A	03/11/99 RAX	Added define removal menuitem.
;R44	03/10/99 RIC	Support 693A DRAM Asynchronous.
;R43	03/04/99 RIC	Don't let the IRQ of Sound Blaster share to other
;			Device because this Sound Blaster is Legacy ISA.
;R42	02/26/98 RIC	Fix that UltraDMA 66 CLK don't be open when UltraDMA
;			66 pluged.
;R41	02/24/99 RIC	Enable AC-Link Variable-Sample-Rate(AC97 Rx41<3>=1)
;R40	02/11/99 RIC	Fix that Hareware RESET cause syetm auto-PowerOff when
;			Power Fail item set 'OFF'.
;			 If you don't want to cover it.
;			    You want to the same as PIIX4, please define:
;			    "PowerFail_As_PIIX4		EQU	1"
;R39 	02/11/99 RIC	Protect RTC 0Dh write for new 686A chip.
;R31A	02/09/99 ADS	Fixe complier error.
;R38	02/05/99 RIC	Latency Time of NorthBridge set to 00h for speeding up
;			UltraDMA 66 performance.
;R37	01/29/99 PAL	Move "SndChip_Cntl_USE_ClkGen" to CLKCNTL.ASM
;R36	01/26/99 RAX	Added PCI slot master control for customer.
;R35	01/19/99 RIC	Fixed that compile fail(out of memory) in pnp.equ of
;			chippost.asm
;R34	01/06/99 RIC	Add "SHOW_ECC_FUNC" definition for ECC status show.
;R33	01/05/99 ADS	Add "Issue_Gemlight_TV_Out_Function" define for customer request. 
;R32	12/28/98 RIC	Modify the CMOS index of the flag of exit form SETUP
;			(F0h => F4h)
;R25A	12/21/98 RIC	Fix that system screen show blank in Win95 shatdown
;			when BIOS Cacheable is enabled.
;R31	12/21/98 RIC	Add "USB2_Separate_Control" define.
;R30	12/21/98 RIC	Support UltraDMA66 HDD in 686/686A SouthBridge.
;			You must define the cable detection Pin of CH1/CH2
;			 UltraDMA66 : 
;			CH1_UltraDMA66_High_In_GPI EQU 1....13
;			CH1_UltraDMA66_Low_In_GPI  EQU 1....13
;			CH2_UltraDMA66_High_In_GPI EQU 1....13
;			CH2_UltraDMA66_Low_In_GPI  EQU 1....13
;	(example)
;	CH1_UltraDMA66_Low_In_GPI EQU 1 ;GPI1 Low mean => CH1 Ultra66
;	CH2_UltraDMA66_Low_In_GPI EQU 3 ;GPI3 Low mean => CH2 Ultra66
;
;R29	12/15/98 RIC	Don't destroy the value of CX in _Set_Ct/X_Set_Ct routine.
;R28	12/11/98 RIC	Add code to control second USB controller On/Off.
;R27A	12/10/98 PAL	Fixed R27 coding error jmp segment call hook method error
;R27 	11/27/98 PAL	Add "SndChip_Cntl_USE_ClkGen" option 
;R26	11/24/98 RIC	Add "HALT_IF_VGA_NOT_FOUND" option. (This option 
;			will be with bug if MONO card plugged only)
;R25	11/19/98 RIC	Add BiosCache_Item feature.
;R24	11/17/98 RIC	Add "GPO_LOW_BEFORE_BOOT"
;			    "GPO_HIGH_BEFORE_BOOT" definition.
;R23	11/16/98 RIC	Fix that exit from setup auto-PowerOff when Power Fail
;			Item set 'Off'.
;R22	11/16/98 RIC	Fix that Trend Anti-Virus replace F0000-F4800 area.
;			So move Get_Set_Ct_OR, Get_Set_Ct_AND to chiprun.
;R21	11/13/98 PAL	Remove E000 shadow control code to PMUPOST.ASM 
;			to avoid Trend code destroy
;R20	11/05/98 RIC	Add "VIA686HM_SUPPORT" definition.
;R19	11/03/98 RIC	Add "GPO_HIGH_BEFORE_BOOT","GPO_LOW_BEFORE_BOOT" define.
;R18	10/26/98 RIC	Fix that the IRQ of SCI assign fail in 
;			new VIA Super SouthBridge VT686.
;R17	10/21/98 RIC	Enable 'Clear DMA Write Flag by IO Write to Port 1F7h/177h'
;			function of IDE of 596 chip.
;			(Fix that OPTI Audio Card have garbage in W95/98)
;R13A	10/19/98 RIC	Fix that R13 code cause system hang at PCI RESET
;			in ITE8671 IO chip.
;R16	10/14/98 RIC	Disable IDE PreFetch when IDE CDROM used.
;R15	10/12/98 RIC	Add "CAS_Latency_Auto" function.
;R04A	10/09/98 RIC	If VT596 is new version , Don't perform 
;			"UltraMode2_No_Set_Mode1" function.
;R14	10/07/98 PAL	Added I2C access code for all SMbus
;R13	10/06/98 RIC	Fix that Garbage IRQ12 of SuperIO cause system can't
;			entry Suspend when no PS2 mouse pluged.
;R12	10/02/98 RIC	Add the function that SDRAM run saft timing when
;			system power on three times fail.
;R11	10/02/98 BAR	Fixed define support " No_Support_4_IDE " 
;			compile error.
;R05A	09/30/98 RIC	Modify "DRAM_Bank_Show_As_SIMM" show algorithm
;R10	09/23/98 RIC	Change ACPI IRQ assign algorithm to Auto-assigned.
;			If you want to use old algorithm, please define:
;			1."No_ACPI_IRQ_Auto_Assign" for disabled new algorithm.
;			2."ACPI_IRQ_Selectable" for enabled old algorithm.
;R09	09/22/98 RIC	Fix that WOL hang in POST 0Dh in some mainboard
;			(with 596 SouthBridge)
;R08	09/15/98 RIC	Change the default of DRAM Timing Item to SDRAM.
;R07A	09/15/98 RIC	Modify algorithm and change definition to 
;			"No_Suggested_SDRAM_CL" from "CAS_Latency_Error_String"
;R07	09/14/98 RIC	Add "CAS_Latency_Error_String" define to show message
;			for SDRAM don't support CAS Latency 2T or not support SPD.
;R06	09/14/98 RIC	Add 'KcMoS' sign for CKCMOS.
;R05	09/11/98 RIC	Add "DRAM_Bank_Show_As_SIMM" define.
;R04	09/08/98 RIC	Re-write E000_IDE_Special_Do.(old file copy to *.908)
;R03	09/04/98 RIC	Fix that new 596 version fail in PCI2.1 Card of HCT7.6.
;R02	09/02/98 RIC	Fix that compile error in no USB case.
;R01	09/01/98 RIC	Add "OEM1_GPO_CNTL" define.
;			    "OEM2_GPO_CNTL"
;			    "OEM3_GPO_CNTL"
;R00    08/24/98 RIC	Initialization.

.386p
		PAGE    56,132
		TITLE   CHIPSET  -- 386/486 EISA ROM/BIOS
	;---------------;
	;   Include	;
	;---------------;
		INCLUDE BIOS.CFG
		INCLUDE POST.EQU
		INCLUDE COMMON.MAC
		INCLUDE POST.MAC
;R48		include CPU.EQU
;R48		include CT_TABLE.EQU
;R35 ifdef	PNP_BIOS
;R35 		include	pnp.equ
;R35 endif;	PNP_BIOS
 	ifdef	PNP_BIOS			;R43
 		include	pnp.equ			;R43
 	endif;	PNP_BIOS			;R43
		INCLUDE CHIPSET.EQU

	;-----------------------;
	;  External Subroutine	;
	;-----------------------;
		;***************;
		;    Kernel	;
		;***************;
		extrn   Get_Cmos:near
		extrn   Set_Cmos:near
		extrn   GetItem_Value:Near
		extrn	F000_Getitem_Value:near
		extrn   X_GetItem_Value:Near
		extrn   GetItem_Cmos:Near
		extrn	XCALL_PROC:near
		extrn	Post_call_proc:near
		extrn	F000_call_proc:near

		extrn	F000_Display_String:near
		extrn	X_Display_String:near
		extrn   Pci_IO_Mem_Init:near
		extrn	F000_Shadow_W:near
		extrn	F000_Shadow_R:near
ifdef   PCI_BUS
		extrn   AGet_CfgSpace_Word:near		;PCI1A.ASM
		extrn   AGet_CfgSpace_BYTE:near		;PCI1A.ASM
		extrn   ASet_CfgSpace_BYTE:near		;PCI1A.ASM
		extrn   AGet_CfgSpace_DWord:near	;PCI1A.ASM
		extrn   ASet_CfgSpace_DWord:near	;PCI1A.ASM
;R49 start
		extrn	F000_Get_CfgSpace_Word:near
		extrn	F000_Set_CfgSpace_Word:near
		extrn	F000_Get_CfgSpace_DWord:near
		extrn	F000_Set_CfgSpace_DWord:near
;R49 end
endif;  PCI_BUS
ifdef	VIA686AIO					;R43
		extrn	Sound_Blaster_Item:near		;R43
		extrn	SB_IRQ_Item:near		;R43
endif;	VIA686AIO					;R43

		;***************;
		;    Chipset	;
		;***************;
		extrn   Get_Ct:near
		extrn   Set_Ct:near
		extrn   Get_Set_Ct:near
		extrn	Get_Set_Ct_OR:near		;R22
		extrn	Get_Set_Ct_AND:near		;R22
		extrn	Get_Set_PMU_OR:near		;R22
		extrn	Get_Set_PMU_AND:near		;R22
		extrn	Get_PMIO:near
		extrn	Set_PMIO:near
		extrn	Get_Set_PMIO:near		
		extrn	Get_Set_PMIO_OR:near		
		extrn	Get_Set_PMIO_AND:near		
		extrn	E000_Get_PMIO:near		
		extrn	E000_Set_PMIO:near		
		extrn	E000_Get_Set_PMIO_OR:near	
		extrn	E000_Get_Set_PMIO:near		
		extrn	E000_Get_Set_PMIO_OR:near	
		extrn	E000_Get_Set_PMIO_AND:near	
ifdef	Have_BankInterleave_Item
  IFDEF	Have_Page_Mode_Item
		extrn   Test_DRAM:near
  ENDIF;Have_Page_Mode_Item
endif;	Have_BankInterleave_Item
		extrn	X_If_100MHz_DRAM_Clock:Near
		extrn	E000_GPO_Pin_Low:near		;R19
		extrn	E000_GPO_Pin_High:near		;R19
		extrn	E000_Read_GPI_Pin:Near		;R30

	;-----------------------;
	;  External Item/Label	;
	;-----------------------;
		;***************;
		;    Kernel	;
		;***************;
ifdef	ACPI_Support
ifdef	Special_ACPI_Table_Update		
		include	acpi.inc
		extrn	FACP_Pointer:near
endif;	Special_ACPI_Table_Update		
endif;	ACPI_Support

		;***************;
		;    Chipset	;
		;***************;

		; Chipset FEAT
		extrn	SDRAM_CL_Item:Near
		extrn	Delay_Trans_Item:near
		extrn   Mem_Hole_Item:near
;R25		extrn   VideoCache_Item:near
		extrn	BiosCache_Item:near		;R25
ifdef	Have_BankInterleave_Item
		extrn	SDRAM_BK_Item:Near
endif;	Have_BankInterleave_Item
;R33 - starts
ifdef Issue_Gemlight_TV_Out_Function	     
		extrn	TV_Out_Mode_Item:near
endif; Issue_Gemlight_TV_Out_Function	     
;R33 - ends
ifdef	Have_Page_Mode_Item
		extrn	DRAM_Page_Mode_Item:Near
endif;	Have_Page_Mode_Item
ifdef	Have_AGP_Item
		extrn   AGP_Item:near
endif;	Have_AGP_Item
                extrn   Aperture_Size_Item:near
ifdef VT586_USB					;R02
		extrn	ONBD_USB_Item:Near
endif ;VT586_USB				;R02
;R02ifdef VT586_USB
;R02		extrn	USB_Legacy_Item:near
;R02endif ;VT586_USB		
		extrn	Bank01_Dram_Timing_Val:Near
		extrn	Bank01_Dram_Timing_Val_:Near
		extrn	Bank23_Dram_Timing_Val:Near
		extrn	Bank23_Dram_Timing_Val_:Near
		extrn	Bank45_Dram_Timing_Val:Near
		extrn	Bank45_Dram_Timing_Val_:Near
		extrn	Bank67_Dram_Timing_Val:Near
		extrn	Bank67_Dram_Timing_Val_:Near
		extrn	UltraMode2_Set_Mode1_Status:Near
    ifdef	USB2_Separate_Control	;R31 - starts
		extrn	ONBD_USB_2_Item:Near
    endif;	USB2_Separate_Control	;R31 - ends
ifndef	No_Have_DRAM_Async_Item				;R44A
		extrn	DRAM_Async_Val_:Near		;R44
endif	;No_Have_DRAM_Async_Item			;R44A

		; PNP FEAT
ifdef	ACPI_Support
		extrn	ACPI_option_Item:Near
;R10  IFNDEF	No_ACPI_IRQ_Selectable
  IFDEF	ACPI_IRQ_Selectable			;R10
		extrn	Assign_ACPI_IRQ_Item:Near
;R10  ENDIF;	No_ACPI_IRQ_Selectable
  ENDIF;ACPI_IRQ_Selectable			;R10
endif;	ACPI_Support


		; PCI FEAT
;R36 start
ifdef	PCISLOT_MASTER_CONTROL
		extrn	PCI_CONFIG1_Item:near
		extrn	PCI_CONFIG2_Item:near
		extrn	PCI_CONFIG3_Item:near
endif	;PCISLOT_MASTER_CONTROL
;R36 end

		; PM FEAT
ifndef	No_Auto_Hidden_Resume_Item
  IFNDEF	Always_ATX_Power
    ifdef	Have_Keyboard_PowerOn_Item
		extrn	KB_Item:Near
    endif;	Have_Keyboard_PowerOn_Item
  IFNDEF	VT596					
    ifdef	Wake_On_EXTSMI0_Support
		extrn	WO_Item:Near
    endif;	Wake_On_EXTSMI0_Support
  ENDIF;	VT596					
		extrn	Ring_Item:Near
		extrn	Alarm_Item:Near
		extrn	Alarm_Timer_Date_Item:Near
		extrn	Alarm_Timer_Hour_Item:Near
		extrn	Alarm_Timer_Min_Item:Near
		extrn	Alarm_Timer_Sec_Item:Near
  ENDIF;	Always_ATX_Power
endif;	No_Auto_Hidden_Resume_Item

		; IO FEAT
		extrn	IDE_PF_Item:near
ifdef   PCI_BUS
		extrn   ONBD_1IDE_Item:near
		extrn	ONBD_2IDE_Item:near
endif;  PCI_BUS
ifdef   NEW_IDE_MODE_3
		extrn   IdeA_Mode_Item:near
		extrn   IdeB_Mode_Item:near
  IFNDEF	ONCHIP_2ND_ALWAYS_DISABLE
	ifdef	Support_4_IDE			;R11
		extrn   IdeC_Mode_Item:near
		extrn   IdeD_Mode_Item:near
	endif;	Support_4_IDE			;R11
  ENDIF;	ONCHIP_2ND_ALWAYS_DISABLE
  IFDEF		Have_IDE_Threshold_Item
		extrn	IDE_Threshold_Item:near
  ENDIF;	Have_IDE_Threshold_Item
endif;   NEW_IDE_MODE_3
ifndef	VT596
  IFDEF	Control_Onchip_By_GPIO_Low
		extrn	ONBD_Chip_Item:near
  ENDIF;Control_Onchip_By_GPIO_Low
else;	VT596					
  IFDEF	Control_Onchip_By_GPO_Low		
		extrn	ONBD_Chip_Item:near	
  ENDIF;Control_Onchip_By_GPO_Low		
  IFDEF	Control_Onchip_By_GPO_High
		extrn	ONBD_Chip_Item:near	
  ENDIF;Control_Onchip_By_GPO_High		
endif;	VT596					
;R27 - start
;R37ifdef	SndChip_Cntl_USE_ClkGen
;R37		extrn	E000_64K_shadow_R:near
;R37endif;	SndChip_Cntl_USE_ClkGen
;R27 - end

G_RAM		SEGMENT USE16 AT 0

		ORG     04H*4
		INCLUDE SEG_0.INC

		ORG     400H
		INCLUDE G_RAM.INC

ifdef	PNP_BIOS			;R43
		ORG	2000h		;R43
		INCLUDE PNPDATA.INC	;R43
endif	;PNP_BIOS			;R43

G_RAM		ENDS

DGROUP		GROUP   FCODE

DGROUP		GROUP   FCODE
FCODE		SEGMENT USE16 PARA PUBLIC 'CODE'
		ASSUME  CS:DGROUP,DS:DGROUP

ifndef  COMPRESS_CODE
		include chipboot.asm
endif   ;COMPRESS_CODE


;[]==============================================================[]
;
; Enable_Linear_Burst: (POST 09h) (CPUPOST.asm INIT_CYRIX )
;
;	Turn on chipset linear burst function to support Cyrix M1 CPU
;
; Saves: SP
; Entry: None
;  Exit: Cy = 0  Support Linear Burst Function
;	 Cy = 1  No Support Linear Burst Function
; Note : 1. Stack Available
;[]==============================================================[]
		Public  Enable_Linear_Burst
Enable_Linear_Burst     Proc    Near
		stc		; No Linear Burst Support
		ret
Enable_Linear_Burst     Endp

;[]==============================================================[]
;
; Ct_Early_Shadow: (POST 0Bh)
;
;	Shadowing system and video BIOS to speedup booting.
;
;Saves:
;
;	All except ax,dx,es,ds,flag
;Input : None
;Output: None
;
;[Notes]
;
;	1. This routine will shadow system BIOS in early stage
;		of POST.
;	2. Stack available
;[]==============================================================[]
		align 4
		public  Ct_Early_Shadow
Ct_Early_Shadow proc    near
ifdef	PCI_BUS
		call	far ptr E000_Ct_Early_Shadow
			 ;Docket is IDE/AGP/other Device initialize

		call    Pci_IO_Mem_Init
endif;	PCI_BUS
		call	far ptr E000_Ct_Early_Shadow_1
;R51 - start
ifdef	GPO_LOW_IF_VIDEO_OK
		push	es
		mov	ax, 0C000h
		mov	es, ax
		cmp	word ptr es:[0],0AA55h
		jne	short VideoFail

		mov	bl, GPO_LOW_IF_VIDEO_OK
		post_func_call	E000_GPO_Pin_Low	;low for on

	VideoFail:
		pop	es			
endif;	GPO_LOW_IF_VIDEO_OK

ifdef	GPO_LOW_IF_MEMORY_OK
		mov	bl, GPO_LOW_IF_MEMORY_OK
		post_func_call	E000_GPO_Pin_Low	;low for on
endif;	GPO_LOW_IF_MEMORY_OK
;R51 -  end
		ret
Ct_Early_Shadow ENDP

;[]==============================================================[]
;CACHE_INIT: (POST 09h)
;	Cache controller initialization after first testing
;	first 64k memory.
;Saves: ALL but flags
;Input: none
;Output:none
;
;[Notes] 1. Stack is available
;	 2. This function can be used to sizing cache size
;[]==============================================================[]
		align 4
		public  Cache_Init
Cache_Init	proc    near