📄 mc68ez328.h
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#ifndef MC68EZ328_H
#define MC68EZ328_H
/*******************************************************************************
*
* Copyright (C) 1998, MOTOROLA INC. All Rights Reserved
*
* FILE NAME : MC68EZ328.h
* DATE CREATED : 10/1/98
*
* DESCRIPTION:
* This is a header file for the MC68EZ328 processor. This header
* file defines the parallel ports, interrupt controller, UART, SPI,
* and watchdog timer. The definitions provide bit access as well as entire
* register access to these peripherals.
*
*******************************************************************************/
/*
* Register definitions for parallel ports
*/
typedef volatile unsigned char PEDIR_REG;
typedef volatile unsigned char PEDATA_REG;
typedef volatile unsigned char PESEL_REG;
typedef volatile unsigned char PDDIR_REG;
typedef volatile unsigned char PDDATA_REG;
typedef volatile unsigned char PDPUEN_REG;
typedef volatile unsigned char PDSEL_REG;
typedef volatile unsigned char PDPOL_REG;
typedef volatile unsigned char PDIRQEN_REG;
typedef volatile unsigned char PDKBEN_REG;
typedef volatile unsigned char PDIQEG_REG;
/*
* Register definitions for interrupt controller
*/
typedef volatile unsigned int IMR_REG;
/*
* Register definitions for UART
*/
typedef struct
{
volatile unsigned short uEn : 1; /* UART enable */
volatile unsigned short rxEn : 1; /* receiver enable */
volatile unsigned short txEn : 1; /* transmitter enable */
volatile unsigned short clkM : 1; /* clock mode selection */
volatile unsigned short pEn : 1; /* parity enable */
volatile unsigned short odd : 1; /* odd parity */
volatile unsigned short stop : 1; /* stop bit transmission */
volatile unsigned short charLen : 1; /* character length (8/7-bit) */
volatile unsigned short odEn : 1; /* old data enable */
volatile unsigned short ctsD : 1; /* CTS delta enable */
volatile unsigned short rxFE : 0; /* receiver full enable */
volatile unsigned short rxHE : 0; /* receiver half enable */
volatile unsigned short rxRE : 1; /* receiver ready enable */
volatile unsigned short txEE : 1; /* transmitter empty enable */
volatile unsigned short txHE : 1; /* transmitter half empty enable */
volatile unsigned short txAE : 1; /* transmitter available for new data */
} _USTCNT_BITS;
typedef union
{
_USTCNT_BITS bits;
volatile unsigned short all;
} USTCNT_REG;
typedef struct
{
volatile unsigned short reserved1 : 2; /* reserved */
volatile unsigned short uClkDir : 1; /* UCLK direction */
volatile unsigned short reserved2 : 1; /* reserved */
volatile unsigned short baudSrc : 1; /* baud source */
volatile unsigned short divide : 3; /* divider for baud generator */
volatile unsigned short reserved3 : 2; /* reserved */
volatile unsigned short prescaler : 6; /* prescaler for baud generator */
} _UBAUD_BITS;
typedef union
{
_UBAUD_BITS bits;
volatile unsigned short all;
} UBAUD_REG;
typedef struct
{
volatile unsigned short fifoFull : 1; /* FIFO full */
volatile unsigned short fifoHalf : 1; /* FIFO half full */
volatile unsigned short dataReady : 1; /* data ready */
volatile unsigned short oldData : 1; /* old data */
volatile unsigned short ovrRun : 1; /* FIFO overrun */
volatile unsigned short frameError : 1; /* frame error */
volatile unsigned short breakC : 1; /* break character */
volatile unsigned short parError : 1; /* parity error */
volatile unsigned short rxData : 8; /* received data */
} _URX_BITS;
typedef union
{
_URX_BITS bits;
volatile unsigned short all;
} URX_REG;
typedef struct
{
volatile unsigned short fifoEmpty : 1; /* FIFO empty */
volatile unsigned short fifoHalf : 1; /* FIFO half empty */
volatile unsigned short txAvail : 1; /* FIFO has slot available */
volatile unsigned short sendBreak : 1; /* Send break character */
volatile unsigned short noCTS : 1; /* ignore CTS */
volatile unsigned short busy : 1; /* transmitter busy */
volatile unsigned short CTSstat : 1; /* CTS status */
volatile unsigned short CTSdelta : 1; /* CTS changed state */
volatile unsigned short txData : 8; /* transmitted data */
} _UTX_BITS;
typedef union
{
_UTX_BITS bits;
volatile unsigned short all;
} UTX_REG;
/*
* Register definitions for SPI
*/
typedef volatile unsigned short SPIMDATA_REG;
typedef struct
{
volatile unsigned short dataRate : 3; /* data rate divider */
volatile unsigned short reserved : 3; /* reserved */
volatile unsigned short enable : 1; /* SPI enable */
volatile unsigned short xch : 1; /* exchange */
volatile unsigned short irq : 1; /* interrupt request */
volatile unsigned short irqEn : 1; /* interrupt request enable */
volatile unsigned short pha : 1; /* phase */
volatile unsigned short pol : 1; /* polarity */
volatile unsigned short bitCount : 4; /* bit count */
} _SPIMCONT_BITS;
typedef union
{
_SPIMCONT_BITS bits;
volatile unsigned short all;
} SPIMCONT_REG;
/* Register definitions for Watchdog Timer */
typedef struct
{
volatile unsigned short reserved1 : 6; /* reserved */
volatile unsigned short cnt : 2; /* counter bits */
volatile unsigned short inf : 1; /* interrupt flag */
volatile unsigned short reserved2 : 5; /* reserved */
volatile unsigned short isel : 1; /* interrupt selection */
volatile unsigned short en : 1; /* watchdog enable */
} _WATCHDOG_BITS;
typedef union
{
_WATCHDOG_BITS bits;
volatile unsigned int all;
} WATCHDOG_REG;
/* Define the parallel port register addresses */
#define PEDIR (*(volatile PEDIR_REG *) 0xFFFFF420)
#define PEDATA (*(volatile PEDATA_REG *) 0xFFFFF421)
#define PESEL (*(volatile PESEL_REG *) 0xFFFFF423)
#define PDDIR (*(volatile PDDIR_REG *) 0xFFFFF418)
#define PDDATA (*(volatile PDDATA_REG *) 0xFFFFF419)
#define PDPUEN (*(volatile PDPUEN_REG *) 0xFFFFF41A)
#define PDSEL (*(volatile PDSEL_REG *) 0xFFFFF41B)
#define PDPOL (*(volatile PDPOL_REG *) 0xFFFFF41C)
#define PDIRQEN (*(volatile PDIRQEN_REG *) 0xFFFFF41D)
#define PDKBEN (*(volatile PDKBEN_REG *) 0xFFFFF41E)
#define PDIQEG (*(volatile PDIQEG_REG *) 0xFFFFF41F)
/* Define the UART peripheral register addresses */
#define USTCNT (*(volatile USTCNT_REG *) 0xFFFFF900)
#define UBAUD (*(volatile UBAUD_REG *) 0xFFFFF902)
#define URX (*(volatile URX_REG *) 0xFFFFF904)
#define UTX (*(volatile UTX_REG *) 0xFFFFF906)
/* Define the SPI peripheral register addresses */
#define SPIMDATA (*(volatile SPIMDATA_REG *) 0xFFFFF800)
#define SPIMCONT (*(volatile SPIMCONT_REG *) 0xFFFFF802)
/* Define the Watchdog Timer peripheral register addresses */
#define WATCHDOG (*(volatile WATCHDOG_REG *) 0xFFFFFB0A)
/* Define interrupt controller register addresses */
#define IMR (*(volatile IMR_REG *) 0xFFFFF304)
/* Bit masks for bits 31-16, other bit definitions found in flexstk.h */
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
/*
* GLOBAL DEFINES
*/
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
#endif /* MC68EZ328_H */
#define M328BASE 0xFFFFF000
/* Interupt register */
//#define IVR *(uchar8 *)(M328BASE+0x300) // Interrupt Vector Reg
#define ICR *(unsigned short *)(M328BASE+0x302) // Interrupt Control Reg
//#define IMR *(unsigned int *)(M328BASE+0x304) // Interrupt Mask Reg
#define IWR *(unsigned int *)(M328BASE+0x308) // Wakeup Enable Reg
#define ISR *(unsigned int *)(M328BASE+0x30C) // Interrupt Status Reg
#define IPR *(unsigned int *)(M328BASE+0x310) // Interrupt Pending Reg
#define DBIRQ_IM_MUART ((unsigned int) 0x00000004) /* UART - 4 */
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