mcf5407_lo.s

一款corefire的bootloader源码 型号 5407 编译环境 c

 /*********************************************************************
 * File:	mcf5407_lo.s
 * Purpose:	Lowest level routines for mcf5407.
 *
 *
 * Copyright:
 *      1999-2000 MOTOROLA, INC. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of Motorola, Inc. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, MOTOROLA 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  Motorola assumes no responsibility for the maintenance and support
 *  of this software
 ********************************************************************/

#ifdef _UNDERSCORE_
#define mcf5407_mbar     _mcf5407_mbar
#define mcf5407_rambar0  _mcf5407_rambar0
#define mcf5407_rambar1	 _mcf5407_rambar1
#define mcf5407_init     _mcf5407_init
#define main             _main
#endif
 
    .extern ___SP_INIT
    .extern VECTOR_TABLE
    .extern mcf5407_mbar
    .extern mcf5407_rambar0
	.extern mcf5407_rambar1
    .extern mcf5407_init
    .extern main
 
    .global asm_startmeup
    .global _asm_startmeup
    .global cpu_cache_flush
    .global _cpu_cache_flush
	.global	_cpu_cache_disable
	.global cpu_cache_disable
	.global	mcf5407_wr_vbr
	.global _mcf5407_wr_vbr
	.global	mcf5407_wr_cacr
	.global _mcf5407_wr_cacr
	.global	mcf5407_wr_acr0
	.global _mcf5407_wr_acr0
	.global	mcf5407_wr_acr1
	.global _mcf5407_wr_acr1
	.global	mcf5407_wr_acr2
	.global _mcf5407_wr_acr2
	.global	mcf5407_wr_acr3
	.global _mcf5407_wr_acr3
	.global	mcf5407_wr_rambar0
	.global _mcf5407_wr_rambar0
	.global	mcf5407_wr_rambar1
	.global _mcf5407_wr_rambar1
	.global	mcf5407_wr_mbar
	.global _mcf5407_wr_mbar





	.equ	SRAMsize,2048-0x10   /* something needs to be changed here */

	.text

/*
 * This is the main entry point upon hard reset.
 */
asm_startmeup:
_asm_startmeup:

	move.w		#0x2700,SR
	move.l      #VECTOR_TABLE,d0
	movec       d0,VBR

	/* Invalidate the cache and disable it */
	move.l	#0x01000000,d0
	dc.l	0x4e7b0002		/* movec d0,cacr */

	/* Disable ACRs */
	moveq.l	#0,d0
	dc.l	0x4e7b0004		/* movec d0,ACR0 */
	dc.l	0x4e7b0005		/* movec d0,ACR1 */
	dc.l	0x4e7b0006		/* movec d0,ACR2 */
	dc.l	0x4e7b0007		/* movec d0,ACR3 */    

	/* Initialize RAMBAR0 */
	move.l	#0xE0000001,d0	/* locate SRAM, validate it! */
	dc.l	0x4e7b0C04		/* movec d0,RAMBAR0 */


	nop
	nop

	/*
	 * Point SP into SRAM (temporarily).  SRAM is used as stack space
	 * while initializing the mcf5407 periphs and memory controller.
	 */
	move.l	#0xE0000000+SRAMsize,SP

	/* Obtain pointer to where MBAR is to be mapped */
	jsr		mcf5407_mbar
	move.l	d0,d6

	/* Obtain pointer to where RAMBAR0 is to be mapped */
	jsr		mcf5407_rambar0

	/* Adjust SP to (soon to be valid) SRAM */
	move.l	d0,a0
	lea		SRAMsize(a0),SP

	/* Map RAMBAR0 and MBAR */
	addq.l	#1,d0			/* Set Valid bit */
	dc.l	0x4e7b0C04		/* movec d0,RAMBAR0 */

	move.l	d6,d0
	addq.l	#1,d0			/* Set Valid bit */
	dc.l	0x4e7b0C0F		/* movec d0,MBAR */

	/* Obtain pointer to where RAMBAR1 is to be mapped */
	jsr		mcf5407_rambar1

	/* Map RAMBAR1 */
	addq.l	#1,d0			/* Set Valid bit */
	dc.l	0x4e7b0C05		/* movec d0,RAMBAR1 */


	/* Initialize mcf5407 periphs, etc */
	move.l	d6,-(sp)		/* pointer to internal resources */
	jsr		mcf5407_init
	lea		4(sp),sp

	/*
	 * Point SP to DRAM.  DRAM may only be visible once CS0 
	 * de-activated as global chipselect.
	 */
	move.l	#___SP_INIT,sp

	nop
	nop

	jmp		main

/********************************************************************
 *	Routine to cleanly flush the cache, pushing all lines and 
 *	invalidating them.  This must be done to change the cache when 
 *	we have been operating in copyback mode (i.e. writes to a copyback 
 *	region are probably resident in the cache and not in the main store).
 */
_cpu_cache_flush:
cpu_cache_flush:
	nop					/* synchronize - flush store buffer */

	moveq.l	#0,d0		/* init line counter */
	moveq.l #0,d1		/* init set counter */
	move.l	d0,a0		/* init An */

flushloop:

 	cpushl	(a0)		/* push cache line a0 - GNU Compiler */
/*	cpushl	bc,(a0) */	/* push cache line a0 - Diab Compiler */

	add.l	#0x0010,a0	/* increment setindex by 1 */
	addq.l	#1,d1		/* increment set counter */
	cmpi.l	#128,d1		/* are sets for this line done? */
	bne		flushloop

	moveq.l	#0,d1		/* set counter to zero again */
	addq.l	#1,d0		/* increment to next line */
	move.l	d0,a0		/* set 0, line d0 into a0 as per cpushl */
	cmpi.l	#4,d0
	bne		flushloop

	rts

/********************************************************************
 *	Routine to disable to cache completely
 *	THIS ROUTINE DISABLES IRQ's -- be warned
 */
_cpu_cache_disable:
cpu_cache_disable:
	nop
	move.w	#0x2700,SR		/* mask off IRQ's */
	jsr		_cpu_cache_flush	/* flush the cache completely */	
	clr.l	d0
	movec	d0,ACR0			/* ACR0 off */
	movec	d0,ACR1			/* ACR1 off */
	movec	d0,ACR2			/* ACR2 off */
	movec	d0,ACR3			/* ACR3 off */

	move.l	#0x01000000,d0	/* Invalidate and disable cache */
	movec	d0,CACR
	rts

/********************************************************************
 * These routines write to the special purpose registers in the ColdFire
 * core.  Since these registers are write-only in the supervisor model,
 * no corresponding read routines exist.
 */
mcf5407_wr_vbr:
_mcf5407_wr_vbr:
	move.l	4(sp),d0
	andi.l	#0xFFF00000,d0	/* align to 1M boundary	 */
	movec	d0,VBR
	nop
	rts

mcf5407_wr_cacr:
_mcf5407_wr_cacr:
    move.l  4(sp),d0
    dc.l    0x4e7b0002      /* movec d0,cacr	 */
    nop
    rts

mcf5407_wr_acr0:
_mcf5407_wr_acr0:
    move.l  4(sp),d0
    dc.l    0x4e7b0004      /* movec d0,ACR0	*/
    nop
    rts

mcf5407_wr_acr1:
_mcf5407_wr_acr1:
    move.l  4(sp),d0
    dc.l    0x4e7b0005      /* movec d0,ACR1	*/
    nop
    rts

mcf5407_wr_acr2:
_mcf5407_wr_acr2:
    move.l  4(sp),d0
    dc.l    0x4e7b0006      /* movec d0,ACR2	*/
    nop
    rts

mcf5407_wr_acr3:
_mcf5407_wr_acr3:
    move.l  4(sp),d0
    dc.l    0x4e7b0007      /* movec d0,ACR3	*/
    nop
    rts

mcf5407_wr_rambar0:
_mcf5407_wr_rambar0:
    move.l  4(sp),d0
    dc.l    0x4e7b0C04      /* movec d0,RAMBAR0	*/
    nop
    rts

mcf5407_wr_rambar1:
_mcf5407_wr_rambar1:
    move.l  4(sp),d0
    dc.l    0x4e7b0C05      /* movec d0,RAMBAR1	*/
    nop
    rts

mcf5407_wr_mbar:
_mcf5407_wr_mbar:
    move.l  4(sp),d0
    dc.l    0x4e7b0C0F      /* movec d0,MBAR	*/
    nop
    rts

	.end