📄 sysinit.c
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return;
}
}
printf("\n");
printf("Congratulations! All SDRAM tests passed!\n");
}
/****************************************************************/
int
probe (uint32 base, uint32 offset)
{
/*
* This routine non-destructively probes a memory address to
* determine if physical memory exists, or if the address
* is shadowed or non-existant at all. A return value of 1
* indicates physical memory (that is not shadowed) exists at
* the address, a return value of 0 indicates that no physical
* memory is present.
*/
uint32 base_orig;
uint32 offset_orig;
uint32 data;
/*
* Step 1) Retain original values of address contents.
*/
base_orig = *(uint32 *)(base);
asm (" nop");
offset_orig = *(uint32 *)(base + offset);
asm (" nop");
/*
* Step 2) Write Pattern 2 to 'offset'
*/
*(uint32 *)(base + offset) = PATTERN_2;
asm (" nop");
/*
* Step 3) Pattern 1 'base' in order to detect shadow.
*/
*(uint32 *)(base) = PATTERN_1;
asm (" nop");
/*
* Step 4) Read 'offset'
*/
data = *(uint32 *)(base + offset);
asm (" nop");
/*
* Step 5) Restore original values
*/
*(uint32 *)(base + offset) = offset_orig;
asm (" nop");
*(uint32 *)(base) = base_orig;
asm (" nop");
if (data == PATTERN_2)
{
/*
* Real physical memory exists at address
*/
return 1;
}
else
{
/*
* No physical memory exists at physical address
*/
return 0;
}
}
/****************************************************************/
void
mcf5407_sim_init (MCF5407_IMM *imm)
{
/*******************************************************
*
* This routine executed upon reset to initialize
* MCF5407 periphs. An initial stack must have been setup
* in the SRAM in order for this routine to work.
*
*******************************************************/
MCF5407_WR_SIM_SYPCR(imm,0); /* Disable the Software Watchdog */
MCF5407_WR_SIM_PAR(imm,0); /* Set all Par Ports to General I/O */
MCF5407_WR_SIM_IRQPAR(imm,0); /* IRQ1,3,5 are Internal Interrupts 1,3,5 */
MCF5407_WR_SIM_PLLCR(imm,0); /* Disable CPU STOP Instruction */
MCF5407_WR_SIM_MPARK(imm,0); /* Disable external visibility of internal bus */
MCF5407_WR_SIM_IMR(imm,0xFFFFFFFF); /* Mask all interrupt sources */
MCF5407_WR_SIM_AVCR(imm,0xFF); /* Autovector all external interrupts */
/*
* Setup Interrupt Source Vectors
*/
MCF5407_WR_SIM_ICR0(imm, 0 /* Software Watchdog */
| MCF5407_SIM_ICR_AVEC
| MCF5407_SIM_ICR_IL(7)
| MCF5407_SIM_ICR_IP_EXT ) ;
MCF5407_WR_SIM_ICR1(imm, 0
| MCF5407_SIM_ICR_AVEC /* Timer 1 */
| MCF5407_SIM_ICR_IL(5)
| MCF5407_SIM_ICR_IP_EXT
| MCF5407_SIM_ICR_IP_INT ) ;
MCF5407_WR_SIM_ICR2(imm, 0
| MCF5407_SIM_ICR_AVEC /* Timer 2 */
| MCF5407_SIM_ICR_IL(5)
| MCF5407_SIM_ICR_IP_INT ) ;
MCF5407_WR_SIM_ICR3(imm, 0
| MCF5407_SIM_ICR_AVEC /* MBUS */
| MCF5407_SIM_ICR_IL(3) ) ;
MCF5407_WR_SIM_ICR4(imm, 0
| MCF5407_SIM_ICR_AVEC /* UART 1 */
| MCF5407_SIM_ICR_IL(3)
| MCF5407_SIM_ICR_IP_EXT ) ;
MCF5407_WR_SIM_ICR5(imm, 0
| MCF5407_SIM_ICR_AVEC /* UART 2 */
| MCF5407_SIM_ICR_IL(3)
| MCF5407_SIM_ICR_IP_INT ) ;
MCF5407_WR_SIM_ICR6(imm, 0
| MCF5407_SIM_ICR_AVEC /* DMA 0 */
| MCF5407_SIM_ICR_IL(2) ) ;
MCF5407_WR_SIM_ICR7(imm, 0
| MCF5407_SIM_ICR_AVEC /* DMA 1 */
| MCF5407_SIM_ICR_IL(2)
| MCF5407_SIM_ICR_IP_INT ) ;
MCF5407_WR_SIM_ICR8(imm, 0
| MCF5407_SIM_ICR_AVEC /* DMA 2 */
| MCF5407_SIM_ICR_IL(2)
| MCF5407_SIM_ICR_IP_EXT ) ;
MCF5407_WR_SIM_ICR9(imm, 0
| MCF5407_SIM_ICR_AVEC /* DMA 3 */
| MCF5407_SIM_ICR_IL(2)
| MCF5407_SIM_ICR_IP_EXT
| MCF5407_SIM_ICR_IP_INT ) ;
MCF5407_WR_SIM_ICR10(imm, 0
| MCF5407_SIM_ICR_AVEC /* unused */
| MCF5407_SIM_ICR_IL(1) ) ;
MCF5407_WR_SIM_ICR11(imm, 0
| MCF5407_SIM_ICR_AVEC /* unused */
| MCF5407_SIM_ICR_IL(1)
| MCF5407_SIM_ICR_IP_EXT ) ;
}
/****************************************************************/
void
mcf5407_pp_init (MCF5407_IMM *imm)
{
MCF5407_WR_PP_PADDR(imm,0); /* Init PADDR to all inputs. */
}
/****************************************************************/
void
mcf5407_mbus_init (MCF5407_IMM *imm)
{
MCF5407_WR_MBUS_MBCR(imm,0); /* Disable MBUS */
}
/****************************************************************/
void
mcf5407_dma_init (MCF5407_IMM *imm)
{
MCF5407_WR_DMA0_DCR(imm,0); /* Disable DMA 0 */
MCF5407_WR_DMA1_DCR(imm,0); /* Disable DMA 1 */
MCF5407_WR_DMA2_DCR(imm,0); /* Disable DMA 2 */
MCF5407_WR_DMA3_DCR(imm,0); /* Disable DMA 3 */
}
/****************************************************************/
void
mcf5407_timer_init (MCF5407_IMM *imm)
{
/* Reset timers and disable them */
MCF5407_WR_TIMER0_TMR(imm,0);
MCF5407_WR_TIMER1_TMR(imm,0);
MCF5407_WR_TIMER0_TER(imm, 0
| MCF5407_TIMER_TER_REF
| MCF5407_TIMER_TER_CAP
) ;
MCF5407_WR_TIMER1_TER(imm, 0
| MCF5407_TIMER_TER_REF
| MCF5407_TIMER_TER_CAP
) ;
}
/****************************************************************/
void
mcf5407_uart_init(MCF5407_IMM *imm)
{
/************************************************************************/
/* UART 0 */
/************************************************************************/
MCF5407_WR_UART0_UCR(imm,MCF5407_UART_UCR_RESET_TX); /* Transmitter Reset */
MCF5407_WR_UART0_UCR(imm,MCF5407_UART_UCR_RESET_RX); /* Receiver Reset */
MCF5407_WR_UART0_UCR(imm,MCF5407_UART_UCR_TX_ENABLED); /* Enable Transmitter */
MCF5407_WR_UART0_UCR(imm,MCF5407_UART_UCR_RX_ENABLED); /* Enable Receiver */
MCF5407_WR_UART0_UCR(imm,MCF5407_UART_UCR_RESET_MR); /* Mode Register Reset */
MCF5407_WR_UART0_UMR(imm, 0
| MCF5407_UART_UMR1_PM_NONE /* No parity */
| MCF5407_UART_UMR1_BC_8 /* 8 bits per character */
) ;
MCF5407_WR_UART0_UMR(imm, 0
| MCF5407_UART_UMR2_CM_NORMAL /* No echo or loopback */
| MCF5407_UART_UMR2_STOP_BITS_1 /* 1 stop bit */
) ;
MCF5407_WR_UART0_UCSR(imm, 0
| MCF5407_UART_UCSR_RCS0
| MCF5407_UART_UCSR_RCS2
| MCF5407_UART_UCSR_RCS3
| MCF5407_UART_UCSR_TCS0
| MCF5407_UART_UCSR_TCS2
| MCF5407_UART_UCSR_TCS3
) ;
MCF5407_WR_UART0_UIMR(imm,0); /* Disable all interrupts */
MCF5407_WR_UART0_UBG1(imm,0);
MCF5407_WR_UART0_UBG2(imm,0x51); /* Set baud to 19200, 50MHZ */
/************************************************************************/
/* UART 2 */
/************************************************************************/
MCF5407_WR_UART1_UCR(imm, 0 /* Disable UART 1 */
| MCF5407_UART_UCR_TX_DISABLED
| MCF5407_UART_UCR_RX_DISABLED
) ;
}
/****************************************************************/
void
mcf5407_cs_init (MCF5407_IMM *imm)
{
/* ChipSelect 2 - SRAM */
MCF5407_WR_CS_CSAR2(imm,0x3000);
MCF5407_WR_CS_CSCR2(imm,0x0100);
MCF5407_WR_CS_CSMR2(imm,(MCF5407_CS_CSMR_MASK_512K | 0x01));
/* ChipSelect 3 - Ethernet */
MCF5407_WR_CS_CSAR3(imm,0x4000);
MCF5407_WR_CS_CSCR3(imm,0x0080);
MCF5407_WR_CS_CSMR3(imm,0x000F0001);
/* ChipSelect 1,4,5,6 and 7 - Invalid */
MCF5407_WR_CS_CSMR1(imm,0);
MCF5407_WR_CS_CSMR4(imm,0);
MCF5407_WR_CS_CSMR5(imm,0);
MCF5407_WR_CS_CSMR6(imm,0);
MCF5407_WR_CS_CSMR7(imm,0);
/* ChipSelect 0 is the global chip select coming out of system
* reset.CS0 is asserted for every access until CSMR0 is written.
* Therefore, the entire ChipSelect must be properly set prior to
* asserting CSMR0_V.
*/
MCF5407_WR_CS_CSAR0(imm, MCF5407_CS_CSAR(FLASH_ADDRESS));
MCF5407_WR_CS_CSCR0(imm,0x0D80);
MCF5407_WR_CS_CSMR0(imm,0x001F0001);
}
/********************************************************************/
/*
* Out of reset, the low-level assembly code calls this routine to
* obtain the address at which to map the MBAR.
*/
void *
mcf5407_mbar (void)
{
return (void *)IMM_ADDRESS;
}
/********************************************************************/
/*
* Out of reset, the low-level assembly code calls this routine to
* obtain the address at which to map the RAMBAR.
*/
void *
mcf5407_rambar0 (void)
{
return (void *)INT_SRAM0_ADDRESS;
}
/********************************************************************/
/*
* Out of reset, the low-level assembly code calls this routine to
* obtain the address at which to map the RAMBAR.
*/
void *
mcf5407_rambar1 (void)
{
return (void *)INT_SRAM1_ADDRESS;
}
/********************************************************************/⌨️ 快捷键说明
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