sysinit.c

一款corefire的bootloader源码 型号 5407 编译环境 c

 /*********************************************************************
 * File:		sysinit.c
 * Purpose:		Power-on Reset configuration of the MCF5407.
 *
 *
 * Copyright:
 *      1999-2000 MOTOROLA, INC. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of Motorola, Inc. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, MOTOROLA 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  Motorola assumes no responsibility for the maintenance and support
 *  of this software
 ********************************************************************/

#include "mcf5407.h"
#include "init.h"

/********************************************************************/

void
mcf5407_init (MCF5407_IMM *imm)
{
	/*******************************************************
	*	Out of reset, the low-level assembly code calls this 
	*	routine to initialize the MCF5407 modules for the  
	*	(M5407AN | M5407C3) board. A temporary stack has been
	*	 setup in the internal SRAM.
	********************************************************/
	extern char __SDRAM_INIT[];
	extern char __DATA_ROM[];
	extern char __DATA_RAM[];
	extern char __DATA_END[];
	extern char __BSS_START[];
	extern char __BSS_END[];
	extern uint32 VECTOR_TABLE[];
	extern uint32 __VECTOR_RAM[];

	uint8 *dp;
	uint8 *sp;
	uint32 n;

	mcf5407_sim_init(imm);
	mcf5407_timer_init(imm);
	mcf5407_pp_init(imm);
	mcf5407_uart_init(imm);
	if (__SDRAM_INIT)
	{
		mcf5407_sdramc_init1(imm);
	}
	mcf5407_mbus_init(imm);
	mcf5407_dma_init(imm);
	mcf5407_cs_init(imm);
	if (__SDRAM_INIT) 
	{
		mcf5407_sdramc_init2(imm);
	}

	/* Enable level 7 interrupt to ColdFire core */
	MCF5407_WR_SIM_IMR(imm, MCF5407_RD_SIM_IMR(imm) & ~MCF5407_SIM_IMR_EINT7);

    /* Invalidate the cache and disable it */
    mcf5407_wr_cacr( 0
		| MCF5407_CACR_DCINVA
		| MCF5407_CACR_BCINVA 
		| MCF5407_CACR_ICINVA);

	/* Copy the vector table to RAM */
	if (__VECTOR_RAM != VECTOR_TABLE)
	{
		for (n = 0; n < 256; n++)
			__VECTOR_RAM[n] = VECTOR_TABLE[n];
	}
    mcf5407_wr_vbr((uint32)__VECTOR_RAM);


	/* Move initialized data from ROM to RAM. */
	if (__DATA_ROM != __DATA_RAM)
	{
		dp = (uint8 *)__DATA_RAM;
		sp = (uint8 *)__DATA_ROM;
		n = __DATA_END - __DATA_RAM;
		while (n--)
			*dp++ = *sp++;
	}
 
	/* Zero uninitialized data */
	if (__BSS_START != __BSS_END)
	{
		sp = (uint8 *)__BSS_START;
		n = __BSS_END - __BSS_START;
		while (n--)
			*sp++ = 0;
	}

    /*
     * Setup ACRs so that if cache is turned on, only SDRAM 
	 * and Flash are cached
     */
    mcf5407_wr_acr0( 0
        | MCF5407_ACR_BASE(SDRAM_ADDRESS)
        | MCF5407_ACR_MASK(0x00000000)
        | MCF5407_ACR_E
		| MCF5407_ACR_CM_00
        | MCF5407_ACR_S_IGNORE
		);

    mcf5407_wr_acr1( 0
        | MCF5407_ACR_BASE(FLASH_ADDRESS)
        | MCF5407_ACR_MASK(0x00000000)
        | MCF5407_ACR_E
		| MCF5407_ACR_CM_00
        | MCF5407_ACR_S_IGNORE
		);

	/* good for detecting NULL dereferences */
	*(uint32 *)(0) = 0;
	
	printf("\n\n");
	switch (MCF5407_RD_SIM_RSR(imm))
	{
		case MCF5407_SIM_RSR_HRST:
			printf("Hard Reset\n");
			break;
		case MCF5407_SIM_RSR_SWTR:
			printf("Software Watchdog Reset\n");
			break;
	}

	MCF5407_WR_SIM_RSR(imm, 0
		| MCF5407_SIM_RSR_HRST 
		| MCF5407_SIM_RSR_SWTR);
}
/*************************************************************/
void
mcf5407_sdramc_init1 (MCF5407_IMM *imm)
{
	/*******************************************************
	* This routine is the first half of the SDRAM Controller
	* initialization.  It sets up all of the configuration
	* information.  We need time for eight refreshes
	* between this program and the second half of the init.
	*******************************************************/

	unsigned junk = 0xA5A59696;

	/********************************************************
	* DRAM Controller Refresh Register calculation:
	*
	* # of bus clocks = (RC + 1) * 16
	* (703.83 bus clocks / 16) - 1 = RC
	* RC = 42.99 = 42 = 0x2A
	********************************************************/

	/* Initialize DRAM Registers: DCR, DACR, DMR */
	MCF5407_WR_DRAMC_DCR(imm,0x8210);

	MCF5407_WR_DRAMC_DACR0(imm,0x00001404);
	MCF5407_WR_DRAMC_DMR0(imm,0x007C0001);

	MCF5407_WR_DRAMC_DACR1(imm,0x00801404);
	MCF5407_WR_DRAMC_DMR1(imm,0x007C0001);
	
	/* Set IP (bit 3) in DACR */
	MCF5407_WR_DRAMC_DACR0(imm,0x0000140C);
	MCF5407_WR_DRAMC_DACR1(imm,0x0080140C);

	/* Write to each bank to initiate precharge */
	*(uint32 *)0x00000000 = junk;
	*(uint32 *)0x00800000 = junk;

	/* Set RE (bit 15) in DACR */
	MCF5407_WR_DRAMC_DACR0(imm,0x00009404);
	MCF5407_WR_DRAMC_DACR1(imm,0x00809404);
}
/****************************************************************/
void
mcf5407_sdramc_init2 (MCF5407_IMM *imm)
{
	/********************************************************
	* This second half of the SDRAM Controller initialization
	* finishes the configuration.
	********************************************************/
	unsigned junk = 0xA5A59696;

	/* Finish the configuration by issuing the IMRS. */
	MCF5407_WR_DRAMC_DACR0(imm,0x00009444);
	MCF5407_WR_DRAMC_DACR1(imm,0x00809444);

	/* Write to the SDRAM Mode Register (see UM pg. 11-34) */
	*(uint32 *)0x00000400 = junk;
	*(uint32 *)0x00800400 = junk;	
}
/****************************************************************/
#define PATTERN_1	(0xA55A9669)
#define PATTERN_2	(0xF0F0F0F0)

void
mcf5407_sdram_test (void)
{
	int i;

	/* Determine if SDRAM is present */
	if (!probe(SDRAM_ADDRESS_BANK0,0x1000))
		printf("SDRAM test failed (probe)!\n");
	if (!probe(SDRAM_ADDRESS_BANK1,0x1000))
		printf("SDRAM test failed (probe)!\n");

	/* Write patterns to entire SDRAM address space (cache off) */
	for (i = 0; i < SDRAM_SIZE; i+=4)
	{
		*(uint32 *)i = (uint32)(0xFFFFFFFF - (5*i));
	}

	printf("Waiting");
	for (i = 0; i < 10000000; i++)
	{
		if ((i % 500000) == 0)
			printf (".");
	}
	printf("\n");

	/* Read patterns back from SDRAM */
	for (i = 0; i < SDRAM_SIZE; i+=4)
	{
		if (*(uint32 *)i != (uint32)(0xFFFFFFFF - (5*i)))
		{
			printf("SDRAM test failed (cache off)!\n");
			asm("	halt");
			return;
		}
	}

	/* Turn cache on in copyback mode: */
	/* Default Cache Mode is non-cacheable */
	mcf5407_wr_cacr( 0
		| MCF5407_CACR_DEC
		| MCF5407_CACR_DESB
		| MCF5407_CACR_DCINVA
		| MCF5407_CACR_DDCM_11
		);
	/* ACR0 caches SDRAM space in copyback mode */
	mcf5407_wr_acr0( 0 
		| MCF5407_ACR_BASE(SDRAM_ADDRESS)
		| MCF5407_ACR_MASK(0x00)
		| MCF5407_ACR_E
		| MCF5407_ACR_S_IGNORE
		| MCF5407_ACR_CM_01
		);

	/* Write patterns to entire SDRAM address space (cache on) */
	for (i = 0; i < SDRAM_SIZE; i+=4)
	{
		*(uint32 *)i = (uint32)(0x0000FFFF + i);
	}

	/* Flush and disable cache */
	cpu_cache_disable();

	printf("Waiting");
	for (i = 0; i < 10000000; i++)
	{
		if ((i % 500000) == 0)
			printf(".");
	}
	printf("\n");

	/* Read patterns back from SDRAM */
	for (i = 0; i < SDRAM_SIZE; i+=4)
	{
		if (*(uint32 *)i != (uint32)(0x0000FFFF + i))
		{
			printf("SDRAM test failed (cache on)!\n");
			asm("	halt");