📄 mcf5407.h
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#define MCF5407_UART_UOP1_RTS (0x01)
#define MCF5407_UART_UOP0_RTS (0x01)
/***********************************************************************/
/* M-BUS Registers */
/***********************************************************************/
#define MCF5407_MBUS_MADR (0x0280)
#define MCF5407_MBUS_MFDR (0x0284)
#define MCF5407_MBUS_MBCR (0x0288)
#define MCF5407_MBUS_MBSR (0x028C)
#define MCF5407_MBUS_MBDR (0x0290)
/* Read access macros for general use */
#define MCF5407_RD_MBUS_MADR(IMMP) Mcf5407_iord(IMMP,MCF5407_MBUS_MADR,8)
#define MCF5407_RD_MBUS_MFDR(IMMP) Mcf5407_iord(IMMP,MCF5407_MBUS_MFDR,8)
#define MCF5407_RD_MBUS_MBCR(IMMP) Mcf5407_iord(IMMP,MCF5407_MBUS_MBCR,8)
#define MCF5407_RD_MBUS_MBSR(IMMP) Mcf5407_iord(IMMP,MCF5407_MBUS_MBSR,8)
#define MCF5407_RD_MBUS_MBDR(IMMP) Mcf5407_iord(IMMP,MCF5407_MBUS_MBDR,8)
/* Write access macros for general use */
#define MCF5407_WR_MBUS_MADR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_MBUS_MADR,8,DATA)
#define MCF5407_WR_MBUS_MFDR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_MBUS_MFDR,8,DATA)
#define MCF5407_WR_MBUS_MBCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_MBUS_MBCR,8,DATA)
#define MCF5407_WR_MBUS_MBSR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_MBUS_MBSR,8,DATA)
#define MCF5407_WR_MBUS_MBDR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_MBUS_MBDR,8,DATA)
#define MCF5407_MBUS_MADR_ADDR(a) (((a)&0xFE)<<0x01) /* Slave Address */
#define MCF5407_MBUS_MFDR_MBC(a) ((a)&0x3F) /* M-Bus Clock Rate */
#define MCF5407_MBUS_MBCR_MEN (0x80) /* M-Bus Enable */
#define MCF5407_MBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */
#define MCF5407_MBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */
#define MCF5407_MBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */
#define MCF5407_MBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */
#define MCF5407_MBUS_MBCR_RSTA (0x04) /* Repeat Start */
#define MCF5407_MBUS_MBSR_MCF (0x80) /* Data Transfer Complete */
#define MCF5407_MBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */
#define MCF5407_MBUS_MBSR_MBB (0x20) /* Bus Busy */
#define MCF5407_MBUS_MBSR_MAL (0x10) /* Arbitration Lost */
#define MCF5407_MBUS_MBSR_SRW (0x04) /* Slave Transmit */
#define MCF5407_MBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */
#define MCF5407_MBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */
/***********************************************************************/
/* Timer Registers */
/***********************************************************************/
#define MCF5407_TIMER0_TMR (0x0140)
#define MCF5407_TIMER0_TRR (0x0144)
#define MCF5407_TIMER0_TCR (0x0148)
#define MCF5407_TIMER0_TCN (0x014C)
#define MCF5407_TIMER0_TER (0x0151)
#define MCF5407_TIMER1_TMR (0x0180)
#define MCF5407_TIMER1_TRR (0x0184)
#define MCF5407_TIMER1_TCR (0x0188)
#define MCF5407_TIMER1_TCN (0x018C)
#define MCF5407_TIMER1_TER (0x0191)
/* Read access macros for general use */
#define MCF5407_RD_TIMER0_TMR(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER0_TMR,16)
#define MCF5407_RD_TIMER0_TRR(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER0_TRR,16)
#define MCF5407_RD_TIMER0_TCR(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER0_TCR,16)
#define MCF5407_RD_TIMER0_TCN(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER0_TCN,16)
#define MCF5407_RD_TIMER0_TER(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER0_TER,8)
#define MCF5407_RD_TIMER1_TMR(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER1_TMR,16)
#define MCF5407_RD_TIMER1_TRR(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER1_TRR,16)
#define MCF5407_RD_TIMER1_TCR(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER1_TCR,16)
#define MCF5407_RD_TIMER1_TCN(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER1_TCN,16)
#define MCF5407_RD_TIMER1_TER(IMMP) Mcf5407_iord(IMMP,MCF5407_TIMER1_TER,8)
/* Write access macros for general use */
#define MCF5407_WR_TIMER0_TMR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_TIMER0_TMR,16,DATA)
#define MCF5407_WR_TIMER0_TRR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_TIMER0_TRR,16,DATA)
#define MCF5407_WR_TIMER0_TCN(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_TIMER0_TCN,16,DATA)
#define MCF5407_WR_TIMER0_TER(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_TIMER0_TER,8,DATA)
#define MCF5407_WR_TIMER1_TMR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_TIMER1_TMR,16,DATA)
#define MCF5407_WR_TIMER1_TRR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_TIMER1_TRR,16,DATA)
#define MCF5407_WR_TIMER1_TCN(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_TIMER1_TCN,16,DATA)
#define MCF5407_WR_TIMER1_TER(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_TIMER1_TER,8,DATA)
#define MCF5407_TIMER_TMR_PS(a) (((a)&0x00FF)<<8) /* Prescaler Value */
#define MCF5407_TIMER_TMR_CE_ANY (0x00C0) /* Capture on Any Edge */
#define MCF5407_TIMER_TMR_CE_FALL (0x0080) /* Capture on Falling Edge */
#define MCF5407_TIMER_TMR_CE_RISE (0x0040) /* Capture on Rising Edge */
#define MCF5407_TIMER_TMR_CE_NONE (0x0000) /* Disable Capture Event */
#define MCF5407_TIMER_TMR_OM (0x0020) /* Output Mode */
#define MCF5407_TIMER_TMR_ORI (0x0010) /* Output Reference Interrupt Enable */
#define MCF5407_TIMER_TMR_FRR (0x0008) /* Restart After Reference Value */
#define MCF5407_TIMER_TMR_CLK_TIN (0x0006) /* TIN is Input Clock Source */
#define MCF5407_TIMER_TMR_CLK_DIV16 (0x0004) /* Sys Clk / 16 is Input Clock Source */
#define MCF5407_TIMER_TMR_CLK_MSCLK (0x0002) /* Sys Clk is Input Clock Source */
#define MCF5407_TIMER_TMR_CLK_STOP (0x0000) /* Stop Count */
#define MCF5407_TIMER_TMR_RST (0x0001) /* Enable Timer */
#define MCF5407_TIMER_TER_REF (0x02) /* Output Reference Event */
#define MCF5407_TIMER_TER_CAP (0x01) /* Capture Event */
/***********************************************************************/
/* DMA Registers */
/***********************************************************************/
#define MCF5407_DMA0_SAR (0x0300)
#define MCF5407_DMA0_DAR (0x0304)
#define MCF5407_DMA0_DCR (0x0308)
#define MCF5407_DMA0_BCR (0x030C)
#define MCF5407_DMA0_DSR (0x0310)
#define MCF5407_DMA0_DIVR (0x0314)
#define MCF5407_DMA1_SAR (0x0340)
#define MCF5407_DMA1_DAR (0x0344)
#define MCF5407_DMA1_DCR (0x0348)
#define MCF5407_DMA1_BCR (0x034C)
#define MCF5407_DMA1_DSR (0x0350)
#define MCF5407_DMA1_DIVR (0x0354)
#define MCF5407_DMA2_SAR (0x0380)
#define MCF5407_DMA2_DAR (0x0384)
#define MCF5407_DMA2_DCR (0x0388)
#define MCF5407_DMA2_BCR (0x038C)
#define MCF5407_DMA2_DSR (0x0390)
#define MCF5407_DMA2_DIVR (0x0394)
#define MCF5407_DMA3_SAR (0x03C0)
#define MCF5407_DMA3_DAR (0x03C4)
#define MCF5407_DMA3_DCR (0x03C8)
#define MCF5407_DMA3_BCR (0x03CC)
#define MCF5407_DMA3_DSR (0x03D0)
#define MCF5407_DMA3_DIVR (0x03D4)
/* Read access macros for general use */
#define MCF5407_RD_DMA0_SAR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA0_SAR,32)
#define MCF5407_RD_DMA0_DAR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA0_DAR,32)
#define MCF5407_RD_DMA0_DCR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA0_DCR,32)
#define MCF5407_RD_DMA0_BCR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA0_BCR,32)
#define MCF5407_RD_DMA0_DSR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA0_DSR,8)
#define MCF5407_RD_DMA0_DIVR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA0_DIVR,8)
#define MCF5407_RD_DMA1_SAR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA1_SAR,32)
#define MCF5407_RD_DMA1_DAR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA1_DAR,32)
#define MCF5407_RD_DMA1_DCR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA1_DCR,32)
#define MCF5407_RD_DMA1_BCR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA1_BCR,32)
#define MCF5407_RD_DMA1_DSR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA1_DSR,8)
#define MCF5407_RD_DMA1_DIVR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA1_DIVR,8)
#define MCF5407_RD_DMA2_SAR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA2_SAR,32)
#define MCF5407_RD_DMA2_DAR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA2_DAR,32)
#define MCF5407_RD_DMA2_DCR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA2_DCR,32)
#define MCF5407_RD_DMA2_BCR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA2_BCR,32)
#define MCF5407_RD_DMA2_DSR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA2_DSR,8)
#define MCF5407_RD_DMA2_DIVR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA2_DIVR,8)
#define MCF5407_RD_DMA3_SAR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA3_SAR,32)
#define MCF5407_RD_DMA3_DAR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA3_DAR,32)
#define MCF5407_RD_DMA3_DCR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA3_DCR,32)
#define MCF5407_RD_DMA3_BCR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA3_BCR,32)
#define MCF5407_RD_DMA3_DSR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA3_DSR,8)
#define MCF5407_RD_DMA3_DIVR(IMMP) Mcf5407_iord(IMMP,MCF5407_DMA3_DIVR,8)
/* Write access macros for general use */
#define MCF5407_WR_DMA0_SAR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA0_SAR,32,DATA)
#define MCF5407_WR_DMA0_DAR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA0_DAR,32,DATA)
#define MCF5407_WR_DMA0_DCR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA0_DCR,32,DATA)
#define MCF5407_WR_DMA0_BCR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA0_BCR,32,DATA)
#define MCF5407_WR_DMA0_DSR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA0_DSR,8,DATA)
#define MCF5407_WR_DMA0_DIVR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA0_DIVR,8,DATA)
#define MCF5407_WR_DMA1_SAR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA1_SAR,32,DATA)
#define MCF5407_WR_DMA1_DAR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA1_DAR,32,DATA)
#define MCF5407_WR_DMA1_DCR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA1_DCR,32,DATA)
#define MCF5407_WR_DMA1_BCR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA1_BCR,32,DATA)
#define MCF5407_WR_DMA1_DSR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA1_DSR,8,DATA)
#define MCF5407_WR_DMA1_DIVR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA1_DIVR,8,DATA)
#define MCF5407_WR_DMA2_SAR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA2_SAR,32,DATA)
#define MCF5407_WR_DMA2_DAR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA2_DAR,32,DATA)
#define MCF5407_WR_DMA2_DCR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA2_DCR,32,DATA)
#define MCF5407_WR_DMA2_BCR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA2_BCR,32,DATA)
#define MCF5407_WR_DMA2_DSR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA2_DSR,8,DATA)
#define MCF5407_WR_DMA2_DIVR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA2_DIVR,8,DATA)
#define MCF5407_WR_DMA3_SAR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA3_SAR,32,DATA)
#define MCF5407_WR_DMA3_DAR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA3_DAR,32,DATA)
#define MCF5407_WR_DMA3_DCR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA3_DCR,32,DATA)
#define MCF5407_WR_DMA3_BCR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA3_BCR,32,DATA)
#define MCF5407_WR_DMA3_DSR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA3_DSR,8,DATA)
#define MCF5407_WR_DMA3_DIVR(IMMP,DATA) Mcf5407_iowr(IMMP,MCF5407_DMA3_DIVR,8,DATA)
#define MCF5407_DMA_DCR_INT (0x80000000) /* Interrupt on Completion */
#define MCF5407_DMA_DCR_EEXT (0x40000000) /* Enable External Request */
#define MCF5407_DMA_DCR_CS (0x20000000) /* Cycle Steal */
#define MCF5407_DMA_DCR_AA (0x10000000) /* Auto Align */
#define MCF5407_DMA_DCR_BWC_DMA (0x00000000) /* Bandwidth: DMA Priority */
#define MCF5407_DMA_DCR_BWC_16384 (0x02000000) /* Bandwidth: 16384 Bytes */
#define MCF5407_DMA_DCR_BWC_32768 (0x04000000) /* Bandwidth: 32768 Bytes */
#define MCF5407_DMA_DCR_BWC_65536 (0x06000000) /* Bandwidth: 65536 Bytes */
#define MCF5407_DMA_DCR_BWC_131072 (0x08000000) /* Bandwidth: 131072 Bytes */
#define MCF5407_DMA_DCR_BWC_262144 (0x0a000000) /* Bandwidth: 262144 Bytes */
#define MCF5407_DMA_DCR_BWC_524288 (0x0c000000) /* Bandwidth: 524288 Bytes */
#define MCF5407_DMA_DCR_BWC_1048576 (0x0e000000) /* Bandwidth: 1048576 Bytes */
#define MCF5407_DMA_DCR_SAA (0x01000000) /* Single Address Access */
#define MCF5407_DMA_DCR_SRW (0x00800000) /* Forces MRW Signal High */
#define MCF5407_DMA_DCR_SINC (0x00400000) /* Source Increment */
#define MCF5407_DMA_DCR_SSIZE_LONG (0x00000000) /* Source Size: Longword */
#define MCF5407_DMA_DCR_SSIZE_BYTE (0x00100000) /* Source Size: Byte */
#define MCF5407_DMA_DCR_SSIZE_WORD (0x00200000) /* Source Size: Word */
#define MCF5407_DMA_DCR_SSIZE_LINE (0x00300000) /* Source Size: Line */
#define MCF5407_DMA_DCR_DINC (0x00080000) /* Destination Increment */
#define MCF5407_DMA_DCR_DSIZE_LONG (0x00000000) /* Destination Size: Longword */
#define MCF5407_DMA_DCR_DSIZE_BYTE (0x00020000) /* Destination Size: Byte */
#define MCF5407_DMA_DCR_DSIZE_WORD (0x00040000) /* Destination Size: Word */
#define MCF5407_DMA_DCR_START (0x00010000) /* Start Transfer */
#define MCF5407_DMA_DCR_AT (0x00008000) /* DMA acknowledge type, asserts only for final transfer */
#define MCF5407_DMA_DSR_CE (0x40) /* Configuration Error */
#define MCF5407_DMA_DSR_BES (0x20) /* Bus Error on Source */
#define MCF5407_DMA_DSR_BED (0x10) /* Bus Error on Destination */
#define MCF5407_DMA_DSR_REQ (0x04) /* Request */
#define MCF5407_DMA_DSR_BSY (0x02) /* Busy */
#define MCF5407_DMA_DSR_DONE (0x01) /* Transaction Done */
/***********************************************************************/
/*
* Define a pointer to the MCF5407 Internal Memory Map
*/
typedef uint8 MCF5407_IMM;
/***********************************************************************/
#endif /* _CPU_MCF5407_H */
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