📄 mcf5407.h
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#define MCF5407_RD_CS_CSAR5(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR5,16)
#define MCF5407_RD_CS_CSMR5(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR5,32)
#define MCF5407_RD_CS_CSCR5(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR5,16)
#define MCF5407_RD_CS_CSAR6(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR6,16)
#define MCF5407_RD_CS_CSMR6(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR6,32)
#define MCF5407_RD_CS_CSCR6(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR6,16)
#define MCF5407_RD_CS_CSAR7(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR7,16)
#define MCF5407_RD_CS_CSMR7(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR7,32)
#define MCF5407_RD_CS_CSCR7(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR7,16)
/* Write access macros for general use */
#define MCF5407_WR_CS_CSAR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR0,16,DATA)
#define MCF5407_WR_CS_CSMR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR0,32,DATA)
#define MCF5407_WR_CS_CSCR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR0,16,DATA)
#define MCF5407_WR_CS_CSAR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR1,16,DATA)
#define MCF5407_WR_CS_CSMR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR1,32,DATA)
#define MCF5407_WR_CS_CSCR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR1,16,DATA)
#define MCF5407_WR_CS_CSAR2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR2,16,DATA)
#define MCF5407_WR_CS_CSMR2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR2,32,DATA)
#define MCF5407_WR_CS_CSCR2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR2,16,DATA)
#define MCF5407_WR_CS_CSAR3(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR3,16,DATA)
#define MCF5407_WR_CS_CSMR3(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR3,32,DATA)
#define MCF5407_WR_CS_CSCR3(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR3,16,DATA)
#define MCF5407_WR_CS_CSAR4(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR4,16,DATA)
#define MCF5407_WR_CS_CSMR4(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR4,32,DATA)
#define MCF5407_WR_CS_CSCR4(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR4,16,DATA)
#define MCF5407_WR_CS_CSAR5(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR5,16,DATA)
#define MCF5407_WR_CS_CSMR5(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR5,32,DATA)
#define MCF5407_WR_CS_CSCR5(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR5,16,DATA)
#define MCF5407_WR_CS_CSAR6(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR6,16,DATA)
#define MCF5407_WR_CS_CSMR6(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR6,32,DATA)
#define MCF5407_WR_CS_CSCR6(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR6,16,DATA)
#define MCF5407_WR_CS_CSAR7(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR7,16,DATA)
#define MCF5407_WR_CS_CSMR7(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR7,32,DATA)
#define MCF5407_WR_CS_CSCR7(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR7,16,DATA)
/* These definitions only exists in the CSMR for Banks 0 and 1. */
#define MCF5407_CS_CSMR_MASK_4G (0xFFFF0000) /* Set Bank to 4G */
#define MCF5407_CS_CSMR_MASK_2G (0x7FFF0000) /* Set Bank to 2G */
#define MCF5407_CS_CSMR_MASK_1G (0x3FFF0000) /* Set Bank to 1G */
#define MCF5407_CS_CSMR_MASK_1024M (0x3FFF0000) /* Set Bank to 1024M */
#define MCF5407_CS_CSMR_MASK_512M (0x1FFF0000) /* Set Bank to 512M */
#define MCF5407_CS_CSMR_MASK_256M (0x0FFF0000) /* Set Bank to 256M */
#define MCF5407_CS_CSMR_MASK_128M (0x07FF0000) /* Set Bank to 128M */
#define MCF5407_CS_CSMR_MASK_64M (0x03FF0000) /* Set Bank to 64M */
#define MCF5407_CS_CSMR_MASK_32M (0x01FF0000) /* Set Bank to 32M */
#define MCF5407_CS_CSMR_MASK_16M (0x00FF0000) /* Set Bank to 16M */
#define MCF5407_CS_CSMR_MASK_8M (0x007F0000) /* Set Bank to 8M */
#define MCF5407_CS_CSMR_MASK_4M (0x003F0000) /* Set Bank to 4M */
#define MCF5407_CS_CSMR_MASK_2M (0x001F0000) /* Set Bank to 2M */
#define MCF5407_CS_CSMR_MASK_1M (0x000F0000) /* Set Bank to 1M */
#define MCF5407_CS_CSMR_MASK_1024K (0x000F0000) /* Set Bank to 1024K */
#define MCF5407_CS_CSMR_MASK_512K (0x00070000) /* Set Bank to 512K */
#define MCF5407_CS_CSMR_MASK_256K (0x00030000) /* Set Bank to 256K */
#define MCF5407_CS_CSMR_MASK_128K (0x00010000) /* Set Bank to 128K */
#define MCF5407_CS_CSMR_MASK_64K (0x00000000) /* Set Bank to 64K */
#define MCF5407_CS_CSMR_CPU (0x00000020) /* CPU and IACK Cycle Mask */
/* The following definitions exist for all Banks 0-7 */
#define MCF5407_CS_CSAR(a) (((a)&0xFFFF0000)>>16) /* Base Address */
#define MCF5407_CS_CSBARx(a) (((a)&0xFF000000)>>24) /* Base for CS2-7 */
#define MCF5407_CS_CSMR_WP (0x00000100) /* Write Protect */
#define MCF5407_CS_CSMR_AM (0x00000040) /* Alternate Master Mask */
#define MCF5407_CS_CSMR_SC (0x00000010) /* Supervisor Code Mask */
#define MCF5407_CS_CSMR_SD (0x00000008) /* Supervisor Data Mask */
#define MCF5407_CS_CSMR_UC (0x00000004) /* User Code Mask */
#define MCF5407_CS_CSMR_UD (0x00000002) /* User Data Mask */
#define MCF5407_CS_CSMR_V (0x00000001) /* Valid Register */
#define MCF5407_CS_CSCR_WS(a) (((a)&0x0F)<<10) /* Wait States */
#define MCF5407_CS_CSCR_AA (0x0100) /* Auto Acknowledge Enable */
#define MCF5407_CS_CSCR_PS_8 (0x0040) /* Port Size: 8-bit */
#define MCF5407_CS_CSCR_PS_16 (0x0080) /* Port Size: 16-bit */
#define MCF5407_CS_CSCR_PS_32 (0x0000) /* Port Size: 32-bit */
#define MCF5407_CS_CSCR_BEM (0x0020) /* Byte Module Enable */
#define MCF5407_CS_CSCR_BSTR (0x0010) /* Burst Read Enable */
#define MCF5407_CS_CSCR_BSTW (0x0008) /* Burst Write Enable */
/**********************************************************************/
/* Parallel Port (General Purpose I/O) Module, PP */
/**********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5407_PP_PADDR (0x0244)
#define MCF5407_PP_PADAT (0x0248)
/* Read access macros for general use */
#define MCF5407_RD_PP_PADDR(IMMP) Mcf5407_iord(IMMP,MCF5407_PP_PADDR,16)
#define MCF5407_RD_PP_PADAT(IMMP) Mcf5407_iord(IMMP,MCF5407_PP_PADAT,16)
/* Write access macros for general use */
#define MCF5407_WR_PP_PADDR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_PP_PADDR,16,DATA)
#define MCF5407_WR_PP_PADAT(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_PP_PADAT,16,DATA)
#define MCF5407_PP_PADDR_15 (0x8000) /* Bit 15 General I/O Output */
#define MCF5407_PP_PADDR_14 (0x4000) /* Bit 14 General I/O Output */
#define MCF5407_PP_PADDR_13 (0x2000) /* Bit 13 General I/O Output */
#define MCF5407_PP_PADDR_12 (0x1000) /* Bit 12 General I/O Output */
#define MCF5407_PP_PADDR_11 (0x0800) /* Bit 11 General I/O Output */
#define MCF5407_PP_PADDR_10 (0x0400) /* Bit 10 General I/O Output */
#define MCF5407_PP_PADDR_9 (0x0200) /* Bit 9 General I/O Output */
#define MCF5407_PP_PADDR_8 (0x0100) /* Bit 8 General I/O Output */
#define MCF5407_PP_PADDR_7 (0x0080) /* Bit 7 General I/O Output */
#define MCF5407_PP_PADDR_6 (0x0040) /* Bit 6 General I/O Output */
#define MCF5407_PP_PADDR_5 (0x0020) /* Bit 5 General I/O Output */
#define MCF5407_PP_PADDR_4 (0x0010) /* Bit 4 General I/O Output */
#define MCF5407_PP_PADDR_3 (0x0008) /* Bit 3 General I/O Output */
#define MCF5407_PP_PADDR_2 (0x0004) /* Bit 2 General I/O Output */
#define MCF5407_PP_PADDR_1 (0x0002) /* Bit 1 General I/O Output */
#define MCF5407_PP_PADDR_0 (0x0001) /* Bit 0 General I/O Output */
#define MCF5407_PP_PADAT_15 (0x8000) /* Bit 15 Current Status */
#define MCF5407_PP_PADAT_14 (0x4000) /* Bit 14 Current Status */
#define MCF5407_PP_PADAT_13 (0x2000) /* Bit 13 Current Status */
#define MCF5407_PP_PADAT_12 (0x1000) /* Bit 12 Current Status */
#define MCF5407_PP_PADAT_11 (0x0800) /* Bit 11 Current Status */
#define MCF5407_PP_PADAT_10 (0x0400) /* Bit 10 Current Status */
#define MCF5407_PP_PADAT_9 (0x0200) /* Bit 9 Current Status */
#define MCF5407_PP_PADAT_8 (0x0100) /* Bit 8 Current Status */
#define MCF5407_PP_PADAT_7 (0x0080) /* Bit 7 Current Status */
#define MCF5407_PP_PADAT_6 (0x0040) /* Bit 6 Current Status */
#define MCF5407_PP_PADAT_5 (0x0020) /* Bit 5 Current Status */
#define MCF5407_PP_PADAT_4 (0x0010) /* Bit 4 Current Status */
#define MCF5407_PP_PADAT_3 (0x0008) /* Bit 3 Current Status */
#define MCF5407_PP_PADAT_2 (0x0004) /* Bit 2 Current Status */
#define MCF5407_PP_PADAT_1 (0x0002) /* Bit 1 Current Status */
#define MCF5407_PP_PADAT_0 (0x0001) /* Bit 0 Current Status */
/**********************************************************************/
/* DRAM Controller Module, DRAMC */
/**********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5407_DRAMC_DCR (0x0100)
#define MCF5407_DRAMC_DACR0 (0x0108)
#define MCF5407_DRAMC_DMR0 (0x010C)
#define MCF5407_DRAMC_DACR1 (0x0110)
#define MCF5407_DRAMC_DMR1 (0x0114)
/* Read access macros for general use */
#define MCF5407_RD_DRAMC_DCR(IMMP) \
Mcf5407_iord(IMMP,MCF5407_DRAMC_DCR,16)
#define MCF5407_RD_DRAMC_DACR0(IMMP) \
Mcf5407_iord(IMMP,MCF5407_DRAMC_DACR0,32)
#define MCF5407_RD_DRAMC_DMR0(IMMP) \
Mcf5407_iord(IMMP,MCF5407_DRAMC_DMR0,32)
#define MCF5407_RD_DRAMC_DACR1(IMMP) \
Mcf5407_iord(IMMP,MCF5407_DRAMC_DACR1,32)
#define MCF5407_RD_DRAMC_DMR1(IMMP) \
Mcf5407_iord(IMMP,MCF5407_DRAMC_DMR1,32)
/* Write access macros for general use */
#define MCF5407_WR_DRAMC_DCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_DRAMC_DCR,16,DATA)
#define MCF5407_WR_DRAMC_DACR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_DRAMC_DACR0,32,DATA)
#define MCF5407_WR_DRAMC_DMR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_DRAMC_DMR0,32,DATA)
#define MCF5407_WR_DRAMC_DACR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_DRAMC_DACR1,32,DATA)
#define MCF5407_WR_DRAMC_DMR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_DRAMC_DMR1,32,DATA)
/* Controls used by both Synchronous and Asynchronous DRAM */
#define MCF5407_DRAMC_DCR_SO (0x8000) /* Synchronous Operation */
#define MCF5407_DRAMC_DCR_NAM (0x2000) /* No Address Multiplexing */
#define MCF5407_DRAMC_DCR_RC(a) ((a)&0x01FF) /* Refresh Count */
#define MCF5407_DRAMC_DACR_BASE(a) ((a)&0xFFFC0000) /* Base Address */
#define MCF5407_DRAMC_DACR_RE (0x00008000) /* Refresh Enable */
#define MCF5407_DRAMC_DACR_PS_32 (0x00000000) /* Port Size: 32-bit */
#define MCF5407_DRAMC_DACR_PS_8 (0x00000010) /* Port Size: 8-bit */
#define MCF5407_DRAMC_DACR_PS_16 (0x00000020) /* Port Size: 16-bit */
#define MCF5407_DRAMC_DCMR_MASK_4G (0xFFFC0000) /* DRAM Size of 4G */
#define MCF5407_DRAMC_DCMR_MASK_2G (0x7FFC0000) /* DRAM Size of 2G */
#define MCF5407_DRAMC_DCMR_MASK_1G (0x3FFC0000) /* DRAM Size of 1G */
#define MCF5407_DRAMC_DCMR_MASK_1024M (0x3FFC0000) /* DRAM Size of 1024M */
#define MCF5407_DRAMC_DCMR_MASK_512M (0x1FFC0000) /* DRAM Size of 512M */
#define MCF5407_DRAMC_DCMR_MASK_256M (0x0FFC0000) /* DRAM Size of 256M */
#define MCF5407_DRAMC_DCMR_MASK_128M (0x07FC0000) /* DRAM Size of 128M */
#define MCF5407_DRAMC_DCMR_MASK_64M (0x03FC0000) /* DRAM Size of 64M */
#define MCF5407_DRAMC_DCMR_MASK_32M (0x01FC0000) /* DRAM Size of 32M */
#define MCF5407_DRAMC_DCMR_MASK_16M (0x00FC0000) /* DRAM Size of 16M */
#define MCF5407_DRAMC_DCMR_MASK_8M (0x007C0000) /* DRAM Size of 8M */
#define MCF5407_DRAMC_DCMR_MASK_4M (0x003C0000) /* DRAM Size of 4M */
#define MCF5407_DRAMC_DCMR_MASK_2M (0x001C0000) /* DRAM Size of 2M */
#define MCF5407_DRAMC_DCMR_MASK_1M (0x000C0000) /* DRAM Size of 1M */
#define MCF5407_DRAMC_DCMR_MASK_1024K (0x00040000) /* DRAM Size of 1024K */
#define MCF5407_DRAMC_DCMR_MASK_512K (0x00000000) /* DRAM Size of 512K */
#define MCF5407_DRAMC_DCMR_WP (0x00000100) /* Write Protect */
#define MCF5407_DRAMC_DCMR_CPU (0x00000040) /* CPU Space Ignored */
#define MCF5407_DRAMC_DCMR_AM (0x00000020) /* Alternate Master Ignored */
#define MCF5407_DRAMC_DCMR_SC (0x00000010) /* Supervisor Code Ignored */
#define MCF5407_DRAMC_DCMR_SD (0x00000008) /* Supervisor Data Ignored */
#define MCF5407_DRAMC_DCMR_UC (0x00000004) /* User Code Ignored */
#define MCF5407_DRAMC_DCMR_UD (0x00000002) /* User Data Ignored */
#define MCF5407_DRAMC_DCMR_V (0x00000001) /* Valid Register */
/* Controls used only by Asynchronous DRAM*/
#define MCF5407_DRAMC_DCR_RRA_2 (0x0000) /* Refresh RAS Asserted 2 Clocks */
#define MCF5407_DRAMC_DCR_RRA_3 (0x0800) /* Refresh RAS Asserted 3 Clocks */
#define MCF5407_DRAMC_DCR_RRA_4 (0x1000) /* Refresh RAS Asserted 4 Clocks */
#define MCF5407_DRAMC_DCR_RRA_5 (0x1800) /* Refresh RAS Asserted 5 Clocks */
#define MCF5407_DRAMC_DCR_RRP_1 (0x0000) /* Refresh RAS Precharged 3 Clks */
#define MCF5407_DRAMC_DCR_RRP_2 (0x0200) /* Refresh RAS Precharged 3 Clks */
#define MCF5407_DRAMC_DCR_RRP_3 (0x0400) /* Refresh RAS Precharged 3 Clks */
#define MCF5407_DRAMC_DCR_RRP_4 (0x0600) /* Refresh RAS Precharged 3 Clks */
#define MCF5407_DRAMC_DACR_CAS_1 (0x00000000) /* CAS Active 1 Clock */
#define MCF5407_DRAMC_DACR_CAS_2 (0x00001000) /* CAS Active 2 Clocks */
#define MCF5407_DRAMC_DACR_CAS_3 (0x00002000) /* CAS Active 3 Clocks */
#define MCF5407_DRAMC_DACR_CAS_4 (0x00003000) /* CAS Active 4 Clocks */
#define MCF5407_DRAMC_DACR_RP_1 (0x00000000) /* RAS Precharge 1 Clock */
#define MCF5407_DRAMC_DACR_RP_2 (0x00000400) /* RAS Precharge 2 Clocks */
#define MCF5407_DRAMC_DACR_RP_3 (0x00000800) /* RAS Precharge 3 Clocks */
#define MCF5407_DRAMC_DACR_RP_4 (0x00000C00) /* RAS Precharge 4 Clocks */
#define MCF5407_DRAMC_DACR_RNCN (0x00000200) /* RAS Negate to CAS Negate */
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