📄 mcf5407.h
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/* Offsets of the registers from the MBAR */
#define MCF5407_SIM_RSR (0x0000)
#define MCF5407_SIM_SYPCR (0x0001)
#define MCF5407_SIM_SWIVR (0x0002)
#define MCF5407_SIM_SWSR (0x0003)
#define MCF5407_SIM_PAR (0x0004)
#define MCF5407_SIM_IRQPAR (0x0006)
#define MCF5407_SIM_PLLCR (0x0008)
#define MCF5407_SIM_MPARK (0x000C)
#define MCF5407_SIM_IPR (0x0040)
#define MCF5407_SIM_IMR (0x0044)
#define MCF5407_SIM_AVCR (0x004B)
#define MCF5407_SIM_ICR0 (0x004C)
#define MCF5407_SIM_ICR1 (0x004D)
#define MCF5407_SIM_ICR2 (0x004E)
#define MCF5407_SIM_ICR3 (0x004F)
#define MCF5407_SIM_ICR4 (0x0050)
#define MCF5407_SIM_ICR5 (0x0051)
#define MCF5407_SIM_ICR6 (0x0052)
#define MCF5407_SIM_ICR7 (0x0053)
#define MCF5407_SIM_ICR8 (0x0054)
#define MCF5407_SIM_ICR9 (0x0055)
#define MCF5407_SIM_ICR10 (0x0056)
#define MCF5407_SIM_ICR11 (0x0057)
/* Read access macros for general use */
#define MCF5407_RD_SIM_RSR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_RSR,8)
#define MCF5407_RD_SIM_SYPCR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_SYPCR,8)
#define MCF5407_RD_SIM_SWIVR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_SWIVR,8)
#define MCF5407_RD_SIM_PAR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_PAR,16)
#define MCF5407_RD_SIM_IRQPAR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_IRQPAR,8)
#define MCF5407_RD_SIM_PLLCR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_PLLCR,8)
#define MCF5407_RD_SIM_MPARK(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_MPARK,8)
#define MCF5407_RD_SIM_IPR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_IPR,32)
#define MCF5407_RD_SIM_IMR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_IMR,32)
#define MCF5407_RD_SIM_AVCR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_AVCR,8)
#define MCF5407_RD_SIM_ICR0(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR0,8)
#define MCF5407_RD_SIM_ICR1(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR1,8)
#define MCF5407_RD_SIM_ICR2(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR2,8)
#define MCF5407_RD_SIM_ICR3(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR3,8)
#define MCF5407_RD_SIM_ICR4(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR4,8)
#define MCF5407_RD_SIM_ICR5(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR5,8)
#define MCF5407_RD_SIM_ICR6(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR6,8)
#define MCF5407_RD_SIM_ICR7(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR7,8)
#define MCF5407_RD_SIM_ICR8(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR8,8)
#define MCF5407_RD_SIM_ICR9(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR9,8)
#define MCF5407_RD_SIM_ICR10(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR10,8)
#define MCF5407_RD_SIM_ICR11(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR11,8)
/* Write access macros for general use */
#define MCF5407_WR_SIM_RSR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_RSR,8,DATA)
#define MCF5407_WR_SIM_SYPCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_SYPCR,8,DATA)
#define MCF5407_WR_SIM_SWIVR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_SWIVR,8,DATA)
#define MCF5407_WR_SIM_SWSR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_SWSR,8,DATA)
#define MCF5407_WR_SIM_PAR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_PAR,16,DATA)
#define MCF5407_WR_SIM_IRQPAR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_IRQPAR,8,DATA)
#define MCF5407_WR_SIM_PLLCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_PLLCR,8,DATA)
#define MCF5407_WR_SIM_MPARK(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_MPARK,8,DATA)
#define MCF5407_WR_SIM_IPR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_IPR,32,DATA)
#define MCF5407_WR_SIM_IMR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_IMR,32,DATA)
#define MCF5407_WR_SIM_AVCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_AVCR,8,DATA)
#define MCF5407_WR_SIM_ICR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR0,8,DATA)
#define MCF5407_WR_SIM_ICR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR1,8,DATA)
#define MCF5407_WR_SIM_ICR2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR2,8,DATA)
#define MCF5407_WR_SIM_ICR3(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR3,8,DATA)
#define MCF5407_WR_SIM_ICR4(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR4,8,DATA)
#define MCF5407_WR_SIM_ICR5(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR5,8,DATA)
#define MCF5407_WR_SIM_ICR6(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR6,8,DATA)
#define MCF5407_WR_SIM_ICR7(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR7,8,DATA)
#define MCF5407_WR_SIM_ICR8(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR8,8,DATA)
#define MCF5407_WR_SIM_ICR9(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR9,8,DATA)
#define MCF5407_WR_SIM_ICR10(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR10,8,DATA)
#define MCF5407_WR_SIM_ICR11(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR11,8,DATA)
#define MCF5407_SIM_RSR_HRST (0x80) /* Hard or System Reset */
#define MCF5407_SIM_RSR_SWTR (0x20) /* Software Watchdog Timer Reset */
#define MCF5407_SIM_SYPCR_SWE (0x80) /* Software Watchdog Enable */
#define MCF5407_SIM_SYPCR_SWRI (0x40) /* SW Reset/Interrupt Select */
#define MCF5407_SIM_SYPCR_SWT_2_9 (0x00) /* SW Timeout: 2^9 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_11 (0x08) /* SW Timeout: 2^11 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_13 (0x10) /* SW Timeout: 2^13 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_15 (0x18) /* SW Timeout: 2^15 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_18 (0x20) /* SW Timeout: 2^18 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_20 (0x28) /* SW Timeout: 2^20 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_22 (0x30) /* SW Timeout: 2^22 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_24 (0x38) /* SW Timeout: 2^24 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWTA (0x04) /* SW Transfer Acknowledge Enable */
#define MCF5407_SIM_SYPCR_SWTAVAL (0x02) /* SW Transfer Acknowledge Valid */
#define MCF5407_SIM_SWSR_55 (0x55) /* Write $55 to SWSR */
#define MCF5407_SIM_SWSR_AA (0xaa) /* Write $AA to SWSR */
#define MCF5407_SIM_PAR_ADDR31 (0x8000) /* Assign Pin as ADDR31 */
#define MCF5407_SIM_PAR_ADDR30 (0x4000) /* Assign Pin as ADDR30 */
#define MCF5407_SIM_PAR_ADDR29 (0x2000) /* Assign Pin as ADDR29 */
#define MCF5407_SIM_PAR_ADDR28 (0x1000) /* Assign Pin as ADDR28 */
#define MCF5407_SIM_PAR_ADDR27 (0x0800) /* Assign Pin as ADDR27 */
#define MCF5407_SIM_PAR_ADDR26 (0x0400) /* Assign Pin as ADDR26 */
#define MCF5407_SIM_PAR_ADDR25 (0x0200) /* Assign Pin as ADDR25 */
#define MCF5407_SIM_PAR_ADDR24 (0x0100) /* Assign Pin as ADDR24 */
#define MCF5407_SIM_PAR_XTIP (0x0080) /* Assign Pin as XTIP */
#define MCF5407_SIM_PAR_DREQ0 (0x0040) /* Assign Pin as DREQ0 */
#define MCF5407_SIM_PAR_DREQ1 (0x0020) /* Assign Pin as DREQ1 */
#define MCF5407_SIM_PAR_TM2 (0x0010) /* Assign Pin as TM2 */
#define MCF5407_SIM_PAR_TM1 (0x0008) /* Assign Pin as TM1 */
#define MCF5407_SIM_PAR_TM0 (0x0004) /* Assign Pin as TM0 */
#define MCF5407_SIM_PAR_TT1 (0x0002) /* Assign Pin as TT1 */
#define MCF5407_SIM_PAR_TT0 (0x0001) /* Assign Pin as TT0 */
#define MCF5407_SIM_IRQPAR_2 (0x80) /* IRQ[5] pin to Int IL 4, not 5 */
#define MCF5407_SIM_IRQPAR_1 (0x20) /* IRQ[3] pin to Int IL 6, not 3 */
#define MCF5407_SIM_IRQPAR_0 (0x10) /* IRQ[1] pin to Int IL 2, not 1 */
#define MCF5407_SIM_PLLCR_ENBSTOP (0x80) /* Enable CPU STOP Instruction */
#define MCF5407_SIM_PLLCR_PLLIPL(a) (((a)&0x07)<<4) /* PLL Wake-up IPL */
#define MCF5407_SIM_MPARK_PARK(a) (((a)&0x03)<<6) /* Default Bus Master */
#define MCF5407_SIM_MPARK_E2MCTRL (0x20) /* EBus to MBus Arbitration */
#define MCF5407_SIM_MPARK_EARBCTRL (0x10) /* SBus to EBus Arbitration */
#define MCF5407_SIM_MPARK_SHOWDATA (0x08) /* Show SBus on EBus */
#define MCF5407_SIM_MPARK_BCR24BIT (0x01) /* BCR is 24 or 16 bit register */
#define MCF5407_SIM_IPR_DMA3 (0x00020000) /* Interrupt Pending DMA3 */
#define MCF5407_SIM_IPR_DMA2 (0x00010000) /* Interrupt Pending DMA2 */
#define MCF5407_SIM_IPR_DMA1 (0x00008000) /* Interrupt Pending DMA1 */
#define MCF5407_SIM_IPR_DMA0 (0x00004000) /* Interrupt Pending DMA0 */
#define MCF5407_SIM_IPR_UART1 (0x00002000) /* Interrupt Pending UART1 */
#define MCF5407_SIM_IPR_UART0 (0x00001000) /* Interrupt Pending UART0 */
#define MCF5407_SIM_IPR_MBUS (0x00000800) /* Interrupt Pending MBUS */
#define MCF5407_SIM_IPR_TIMER1 (0x00000400) /* Interrupt Pending TIMER1 */
#define MCF5407_SIM_IPR_TIMER0 (0x00000200) /* Interrupt Pending TIMER0 */
#define MCF5407_SIM_IPR_SWT (0x00000100) /* Interrupt Pending SWT */
#define MCF5407_SIM_IPR_EINT7 (0x00000080) /* Interrupt Pending EINT7 */
#define MCF5407_SIM_IPR_EINT6 (0x00000040) /* Interrupt Pending EINT6 */
#define MCF5407_SIM_IPR_EINT5 (0x00000020) /* Interrupt Pending EINT5 */
#define MCF5407_SIM_IPR_EINT4 (0x00000010) /* Interrupt Pending EINT4 */
#define MCF5407_SIM_IPR_EINT3 (0x00000008) /* Interrupt Pending EINT3 */
#define MCF5407_SIM_IPR_EINT2 (0x00000004) /* Interrupt Pending EINT2 */
#define MCF5407_SIM_IPR_EINT1 (0x00000002) /* Interrupt Pending EINT1 */
#define MCF5407_SIM_IMR_DMA3 (0x00020000) /* Mask DMA3 */
#define MCF5407_SIM_IMR_DMA2 (0x00010000) /* Mask DMA2 */
#define MCF5407_SIM_IMR_DMA1 (0x00008000) /* Mask DMA1 */
#define MCF5407_SIM_IMR_DMA0 (0x00004000) /* Mask DMA0 */
#define MCF5407_SIM_IMR_UART1 (0x00002000) /* Mask UART1 */
#define MCF5407_SIM_IMR_UART0 (0x00001000) /* Mask UART0 */
#define MCF5407_SIM_IMR_MBUS (0x00000800) /* Mask MBUS */
#define MCF5407_SIM_IMR_TIMER1 (0x00000400) /* Mask TIMER1 */
#define MCF5407_SIM_IMR_TIMER0 (0x00000200) /* Mask TIMER0 */
#define MCF5407_SIM_IMR_SWT (0x00000100) /* Mask SWT */
#define MCF5407_SIM_IMR_EINT7 (0x00000080) /* Mask EINT7 */
#define MCF5407_SIM_IMR_EINT6 (0x00000040) /* Mask EINT6 */
#define MCF5407_SIM_IMR_EINT5 (0x00000020) /* Mask EINT5 */
#define MCF5407_SIM_IMR_EINT4 (0x00000010) /* Mask EINT4 */
#define MCF5407_SIM_IMR_EINT3 (0x00000008) /* Mask EINT3 */
#define MCF5407_SIM_IMR_EINT2 (0x00000004) /* Mask EINT2 */
#define MCF5407_SIM_IMR_EINT1 (0x00000002) /* Mask EINT1 */
#define MCF5407_SIM_AVCR_AVEC7 (0x80) /* Auto Vector Ext Interrupt 7 */
#define MCF5407_SIM_AVCR_AVEC6 (0x40) /* Auto Vector Ext Interrupt 6 */
#define MCF5407_SIM_AVCR_AVEC5 (0x20) /* Auto Vector Ext Interrupt 5 */
#define MCF5407_SIM_AVCR_AVEC4 (0x10) /* Auto Vector Ext Interrupt 4 */
#define MCF5407_SIM_AVCR_AVEC3 (0x08) /* Auto Vector Ext Interrupt 3 */
#define MCF5407_SIM_AVCR_AVEC2 (0x04) /* Auto Vector Ext Interrupt 2 */
#define MCF5407_SIM_AVCR_AVEC1 (0x02) /* Auto Vector Ext Interrupt 1 */
#define MCF5407_SIM_AVCR_BLK (0x01) /* Block Address Strobe */
#define MCF5407_SIM_ICR_AVEC (0x80) /* Autovector Enable */
#define MCF5407_SIM_ICR_IL(a) (((a)&0x07)<<2) /* Interrupt Level */
#define MCF5407_SIM_ICR_IP_EXT (0x02) /* High Priority External */
#define MCF5407_SIM_ICR_IP_INT (0x01) /* High Priority Internal */
/**********************************************************************/
/* Chip-Select Module, CS */
/**********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5407_CS_CSAR0 (0x0080)
#define MCF5407_CS_CSMR0 (0x0084)
#define MCF5407_CS_CSCR0 (0x008A)
#define MCF5407_CS_CSAR1 (0x008C)
#define MCF5407_CS_CSMR1 (0x0090)
#define MCF5407_CS_CSCR1 (0x0096)
#define MCF5407_CS_CSAR2 (0x0098)
#define MCF5407_CS_CSMR2 (0x009C)
#define MCF5407_CS_CSCR2 (0x00A2)
#define MCF5407_CS_CSAR3 (0x00A4)
#define MCF5407_CS_CSMR3 (0x00A8)
#define MCF5407_CS_CSCR3 (0x00AE)
#define MCF5407_CS_CSAR4 (0x00B0)
#define MCF5407_CS_CSMR4 (0x00B4)
#define MCF5407_CS_CSCR4 (0x00BA)
#define MCF5407_CS_CSAR5 (0x00BC)
#define MCF5407_CS_CSMR5 (0x00C0)
#define MCF5407_CS_CSCR5 (0x00C6)
#define MCF5407_CS_CSAR6 (0x00C8)
#define MCF5407_CS_CSMR6 (0x00CC)
#define MCF5407_CS_CSCR6 (0x00D2)
#define MCF5407_CS_CSAR7 (0x00D4)
#define MCF5407_CS_CSMR7 (0x00D8)
#define MCF5407_CS_CSCR7 (0x00DE)
/* Read access macros for general use */
#define MCF5407_RD_CS_CSAR0(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR0,16)
#define MCF5407_RD_CS_CSMR0(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR0,32)
#define MCF5407_RD_CS_CSCR0(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR0,16)
#define MCF5407_RD_CS_CSAR1(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR1,16)
#define MCF5407_RD_CS_CSMR1(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR1,32)
#define MCF5407_RD_CS_CSCR1(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR1,16)
#define MCF5407_RD_CS_CSAR2(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR2,16)
#define MCF5407_RD_CS_CSMR2(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR2,32)
#define MCF5407_RD_CS_CSCR2(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR2,16)
#define MCF5407_RD_CS_CSAR3(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR3,16)
#define MCF5407_RD_CS_CSMR3(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR3,32)
#define MCF5407_RD_CS_CSCR3(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR3,16)
#define MCF5407_RD_CS_CSAR4(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR4,16)
#define MCF5407_RD_CS_CSMR4(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR4,32)
#define MCF5407_RD_CS_CSCR4(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR4,16)
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