mcf5407.h

一款corefire的bootloader源码 型号 5407 编译环境 c

 /*********************************************************************
 * File:		cpu/MCF5200/MCF5407.h
 * Purpose:		MCF5407 definitions
 *
 *
 * Copyright:
 *      1999-2000 MOTOROLA, INC. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of Motorola, Inc. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, MOTOROLA 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  Motorola assumes no responsibility for the maintenance and support
 *  of this software
 ********************************************************************/

#ifndef _CPU_MCF5407_H
#define _CPU_MCF5407_H

/***********************************************************************/
/*
 * Misc. Defines
 */

#ifdef	FALSE
#undef	FALSE
#endif
#define FALSE	(0)

#ifdef	TRUE
#undef	TRUE
#endif
#define	TRUE	(1)

#ifdef	NULL
#undef	NULL
#endif
#define NULL	(0)

/***********************************************************************/
/*
 * The basic data types
 */

typedef unsigned char		uint8;  /*  8 bits */
typedef unsigned short int	uint16; /* 16 bits */
typedef unsigned long int	uint32; /* 32 bits */

typedef signed char			int8;   /*  8 bits */
typedef signed short int	int16;  /* 16 bits */
typedef signed long int		int32;  /* 32 bits */

/***********************************************************************/
/*
 * Common M68K & ColdFire definitions
 */

#define ADDRESS			uint32
#define INSTRUCTION		uint16
#define ILLEGAL			0x4AFC
#define CPU_WORD_SIZE	16

/***********************************************************************/

/*
 * Routines and macros for accessing Input/Output devices
 */

#define cpu_iord_8(ADDR)        *((volatile uint8 *)(ADDR))
#define cpu_iord_16(ADDR)       *((volatile uint16 *)(ADDR))
#define cpu_iord_32(ADDR)       *((volatile uint32 *)(ADDR))

#define cpu_iowr_8(ADDR,DATA)   *((volatile uint8 *)(ADDR)) = (DATA)
#define cpu_iowr_16(ADDR,DATA)  *((volatile uint16 *)(ADDR)) = (DATA)
#define cpu_iowr_32(ADDR,DATA)  *((volatile uint32 *)(ADDR)) = (DATA)

/***********************************************************************/

#define MCF5200_SR_T		(0x8000)
#define MCF5200_SR_S		(0x2000)
#define MCF5200_SR_M		(0x1000)
#define MCF5200_SR_IPL		(0x0700)
#define MCF5200_SR_IPL_0	(0x0000)
#define MCF5200_SR_IPL_1	(0x0100)
#define MCF5200_SR_IPL_2	(0x0200)
#define MCF5200_SR_IPL_3	(0x0300)
#define MCF5200_SR_IPL_4	(0x0400)
#define MCF5200_SR_IPL_5	(0x0500)
#define MCF5200_SR_IPL_6	(0x0600)
#define MCF5200_SR_IPL_7	(0x0700)
#define MCF5200_SR_X		(0x0010)
#define MCF5200_SR_N		(0x0008)
#define MCF5200_SR_Z		(0x0004)
#define MCF5200_SR_V		(0x0002)
#define MCF5200_SR_C		(0x0001)

/***********************************************************************/

/*
 * The ColdFire family of processors has a simplified exception stack
 * frame that looks like the following:
 *
 *              3322222222221111 111111
 *              1098765432109876 5432109876543210
 *           8 +----------------+----------------+
 *             |         Program Counter         |
 *           4 +----------------+----------------+
 *             |FS/Fmt/Vector/FS|      SR        |
 *   SP -->  0 +----------------+----------------+
 *
 * The stack self-aligns to a 4-byte boundary at an exception, with
 * the FS/Fmt/Vector/FS field indicating the size of the adjustment
 * (SP += 0,1,2,3 bytes).
 */

#define MCF5200_RD_SF_FORMAT(PTR)	\
	((*((uint16 *)(PTR)) >> 12) & 0x00FF)

#define MCF5200_RD_SF_VECTOR(PTR)	\
	((*((uint16 *)(PTR)) >>  2) & 0x00FF)

#define MCF5200_RD_SF_FS(PTR)		\
	( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )

#define MCF5200_SF_SR(PTR)	*((uint16 *)(PTR)+1)
#define MCF5200_SF_PC(PTR)	*((uint32 *)(PTR)+1)

#if 0
typedef struct
{
	uint16	SR;
	uint16	FS_FMT_VECTOR_FS;
	uint32	PC;
} MCF5200_STACK_FRAME;
#endif

/*********************************************************************
 *	Function Prototypes
 *********************************************************************/

void
mcf5407_wr_vbr (uint32);

void
mcf5407_wr_cacr (uint32);

void
mcf5407_wr_acr0 (uint32);

void
mcf5407_wr_acr1 (uint32);

void
mcf5407_wr_rambar0 (uint32);

void
mcf5407_wr_rambar1 (uint32);

void
mcf5407_wr_mbar (uint32);

/**********************************************************************/
/*	Macro for computing address of on-chip peripheral registers		  */
/**********************************************************************/
 
#define Mcf5407_addr(IMMP,OFFSET)	((void *)&((uint8 *)IMMP)[OFFSET])

/**********************************************************************/
/*	Macros for accessing the on-chip I/O resources					  */
/**********************************************************************/
 
#define Mcf5407_iord(IMMP,OFFSET,SIZE)		\
    *(volatile uint ## SIZE *)(Mcf5407_addr(IMMP,OFFSET))

#define Mcf5407_iowr(IMMP,OFFSET,SIZE,DATA)  \
    *(volatile uint ## SIZE *)(Mcf5407_addr(IMMP,OFFSET)) = (DATA)

/**********************************************************************/
/*	Cache and Access Control Register routines and defintions         */
/**********************************************************************/
 
#define MCF5407_CACR_DEC		(0x80000000)	/* Data Cache Enable */
#define MCF5407_CACR_DW			(0x40000000)	/* Data default Write-protect */
#define MCF5407_CACR_DESB		(0x20000000)	/* Data Enable Store Buffer */		    
#define MCF5407_CACR_DDPI		(0x10000000)	/* Data Disable CPUSHL Invalidation */ 	
#define MCF5407_CACR_DHLCK		(0x08000000)	/* 1/2 Data Cache Lock Mode */
#define MCF5407_CACR_DDCM_00	(0x00000000)	/* Cacheable writethrough imprecise */	    
#define MCF5407_CACR_DDCM_01	(0x02000000)	/* Cacheable copyback */		    
#define MCF5407_CACR_DDCM_10	(0x04000000)	/* Noncacheable precise */    
#define MCF5407_CACR_DDCM_11	(0x06000000)	/* Noncacheable imprecise */ 
#define MCF5407_CACR_DCINVA		(0x01000000)	/* Data Cache Invalidate All */ 	    
#define MCF5407_CACR_BEC		(0x00080000)	/* Branch Cache Enable */
#define MCF5407_CACR_BCINVA		(0x00040000)	/* Branch Cache Invalidate All */  

#define MCF5407_CACR_IEC		(0x00008000)	/* Instruction Cache Enable */
#define MCF5407_CACR_IDPI		(0x00001000)	/* Instruction Disable CPUSHL Invalidation */
#define MCF5407_CACR_IHLCK		(0x00000800)	/* 1/2 Instruction Cache Lock Mode */
#define MCF5407_CACR_IDCM		(0x00000400)	/* Instruction default cache mode (Noncacheable) */
#define MCF5407_CACR_ICINVA		(0x00000100)	/* Instruction Cache Invalidate All */ 


#define MCF5407_ACR_BASE(a)	((a)&0xFF000000)	/* Address Base */				
#define MCF5407_ACR_MASK(a)	(((a)&0xFF000000)>>8)	/* Address Mask */		    
#define MCF5407_ACR_E		(0x00008000)		/* Enable */						
#define MCF5407_ACR_S_USER	(0x00000000)		/* User Mode Access */				
#define MCF5407_ACR_S_SUPER	(0x00002000)		/* Supervisor Mode Access */	    
#define MCF5407_ACR_S_IGNORE	(0x00004000)	/* Ignore Mode Access */	    
#define MCF5407_ACR_CM_00	(0x00000000)		/* Cacheable, writethrough */	    
#define MCF5407_ACR_CM_01	(0x00000020)		/* Cacheable, copyback */		    
#define MCF5407_ACR_CM_10	(0x00000040)		/* Cache-Inhibited, precise */	    
#define MCF5407_ACR_CM_11	(0x00000060)		/* Cache-Inhibited, imprecise */	
#define MCF5407_ACR_WP		(0x00000004)		/* Write Protect */				

#define MCF5407_VBR_BASE(a)	((a)&0xFFF00000)	/* Vector Base Address */	    

#define MCF5407_RAMBAR_BASE(a)	((a)&0xFFFFF800)	/* Base Address */		    
#define MCF5407_RAMBAR_WP		(0x00000100)		/* Write Protect */
#define MCF5407_RAMBAR_DI		(0x00000080)		/* Memory assigned to Data(0) or Instruction(1) */		    
#define MCF5407_RAMBAR_AS_CPU	(0x00000020)	/* CPU Space/Interrupt acknowledge */  
#define MCF5407_RAMBAR_AS_SC	(0x00000010)	/* Supervisor Code */		    
#define MCF5407_RAMBAR_AS_SD	(0x00000008)	/* Supervisor Data */		    
#define MCF5407_RAMBAR_AS_UC	(0x00000004)	/* User Code */			    
#define MCF5407_RAMBAR_AS_UD	(0x00000002)	/* User Data */			    
#define MCF5407_RAMBAR_V		(0x00000001)	/* Valid */ 					

#define MCF5407_MBAR_BASE(a)	((a)&0xFFFFF000)	/* Base Address */		    
#define MCF5407_MBAR_WP		(0x00000100)		/* Write Protect */	
#define MCF5407_MBAR_AM		(0x00000040)		/* Alternate master mask */
#define MCF5407_MBAR_CI		(0x00000020)		/* Mask CPU space and interrupt acknowledge cycles */
#define MCF5407_MBAR_SC		(0x00000010)		/* Mask Supervisor Code Space */	
#define MCF5407_MBAR_SD		(0x00000008)		/* Mask Supervisor Data Space */	
#define MCF5407_MBAR_UC		(0x00000004)		/* Mask User Code Space */		    
#define MCF5407_MBAR_UD		(0x00000002)		/* Mask User Data Space	*/	    
#define MCF5407_MBAR_V		(0x00000001)		/* Valid */						

/**********************************************************************/
/*	System Integration Modules, SIM									  */
/**********************************************************************/