📄 3574_78.s43
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;************************************************************************
; MSP430F149 Demo - SPI Communication with TLC3544/48 or TLC3574/78 EVM
; Program implements a digital filter - takes the average of 4 samples
; from CH0 of the ADC and returns them to the TLV5636 DAC
;
; TLC3544/48 MSP430F149
; ------------- -------------
; | SDI|<---|P3.1 |
; | SDO|--->|P3.2 |
; CH0~~>|IN+ SCLK|<---|P3.3 |
; | /CS|<---|P3.5 |
; | FS|<---|P3.6 |
; | CSTART|<---|P3.7 |
; | INT|--->|P1.1 |
; | |
; | |
; TLV5636 DAC | |
; _____________ | |
; | SDI|<---|P3.2 |
; | /CS|--->|P3.5 |
; | FS|--->|P1.6(via PLD)|
;
; Assembled with IAR Embedded Workshop for MSP430 Kickstart
;
; Texas Instruments, Inc.
; Tom Hendrick
; Data Aquisition Applications - Dallas
; Dec. 2000
;************************************************************************
#include "msp430x14x.h" // Standard Equations
#include "TLC357X.h" // ADC Equations
;************************************************************************
;Constants
;************************************************************************
CS equ 020h ; Assign p3.5 to CS
FS equ 040h ; Assign p3.6 to FS
CSTART equ 080h ; Assign p3.7 to CSTART
Samples equ 004h ; Number of Sample for Filter
;************************************************************************
;Setup RAM
;************************************************************************
RSEG UDATA0
ADC_Data DS 0 ; Storage for ADC Samples
;************************************************************************
;Setup Stack
;************************************************************************
RSEG CSTACK
DS 0
;************************************************************************
;Program Code
;************************************************************************
RSEG CODE
;************************************************************************
RESET_ISR mov #SFE(CSTACK),SP ; define stackpointer
call #Init_Sys ; Initialize the MSP430
call #SETUP_ADC ; Initialize the ADC
call #Mainloop ; Run the Main Program
Mainloop
mov.b #Samples, R10 ; Move the # of samples required to R10
mov #00, R8 ; Clear R8
SampleLoop
bic.b #CS,&P3OUT ; Enable TLC3544/48
bis.b #01h,&P1OUT ; Set a test bit - Bit is cleared in ISR
Read_ADC
mov.b #CH0,&U0TXBUF ; Dummy write to SPI (generates SCLK)
call #CLEAR
mov.b &U0RXBUF,ADC_Data(R8) ; Store Upper Byte
inc R8 ; Increment data storage pointer
mov.b #DUMMY,&U0TXBUF ; Dummy write to SPI (generates SCLK)
call #CLEAR
mov.b &U0RXBUF,ADC_Data(R8) ; Store Lower Byte
inc R8 ; Increment data storage pointer
TEST: mov.b #DUMMY,&U0TXBUF ; Dummy write to SPI
call #CLEAR
bit.b #01h, &P1OUT ; Test bit - keep writing 0's to port
jnz TEST ; until an interrupt occurs
dec R10
cmp #00,R10 ; Finished taking sample?
jnz SampleLoop ; Repeat till R10 = 0
; jmp Mainloop ; Repeat
; Remove remark from above line to skip transmit back to DAC
Write_DAC mov #0x0000, R13
mov #Samples, R10
mov #0x0000, R8
next mov ADC_Data(R8), R12
swpb R12 ; Swap Bytes
and.w #0xFFF0, R12 ; Strip trailing bits
rrc.w R12 ; Shift data 4 places
rrc.w R12 ; to conform to
rrc.w R12 ; DAC input format
rrc.w R12 ; Data is shifted!
and.w #0x0FFF, R12 ; Strip any carries
add.w R12, R13
incd R8
dec R10
cmp #00, R10
jnz next
rrc.w R13 ; Divide by 2
rrc.w R13 ; Divide by 2 again
and.w #0x0FFF, R13 ; Strip any carries
add.w #0x4000, R13 ; Set DAC Fast Mode, 0x4000
bic.b #FS,&P3OUT ; toggle Frame Sync
bis.b #FS,&P3OUT ; toggle Frame Sync
bic.b #FS,&P3OUT ; to DAC
swpb R13 ; Align MSB First
mov.b R13,&U0TXBUF ; Transmit upper Data Byte to DAC
call #CLEAR
swpb R13 ; Prepare Lower Byte
mov.b R13,&U0TXBUF ; Transmit lower Data Byte to DAC
call #CLEAR
bis.b #FS,&P3OUT ; Set Frame Sync
jmp Mainloop ; Repeat
;*******************************
; Clear TX Flag
;*******************************
CLEAR
bit.b #UTXIFG0,&IFG1 ; Thank You Eric! TXBUF ready?
jnc CLEAR ; 1 = ready
bic.b #UTXIFG0,&IFG1
ret
;************************************************************************
Init_Sys; Modules and Controls Registers set-up subroutine
;************************************************************************
StopWDT mov #WDTPW+WDTHOLD,&WDTCTL ; Stop Watchdog Timer
SetupClock
bic.b #XTOFF, &BCSCTL1
bis.b #SELM1+SELS, &BCSCTL2
HF_WAIT ; 8MHz Crystal used - wait for stabilization
bic.b #OFIFG, &IFG1
bit.b #OFIFG, &IFG1
jnz HF_WAIT
bic.b #OFIFG, &IFG1 ; Clear Oscillator fault flag
bit.b #OFIFG, &IFG1 ; Test for clear
SetupPort
bis.b #001h,&P1DIR ; P1 pin 1 set to output (toggle's LED)
bis.b #01Eh,&P3SEL ; P3.1,2,3,4 SPI option select
bis.b #CS+FS+CSTART,&P3DIR ; /CS, FS & CSTART = P3 output direction
bis.b #CS+FS+CSTART,&P3OUT ; P3.5,6,7 CS & FS set
SetupInterrupt
bic.b #02h, &P1IFG ; Clear interrupt flags
bis.b #02h, &P1IES ; Set for edge selection
bis.b #02h, &P1IE ; Enable external Interrupt
SetupSPI
bis.b #040h,&ME1 ; Enable SPI TX/RX
mov.b #CHAR+SYNC+MM,&U0CTL ; 8-bit SPI Master
bis.b #SSEL0+SSEL1+STC,&U0TCTL
mov.b #02h,&U0BR0 ; Set SPI Baud Rate
mov.b #00h,&U0BR1 ; This give 4MHz SCLK w/ 8MHz Crystal
mov.b #00h,&U0MCTL
eint ; Enable interrupts
ret
;*********************************************************************************
SETUP_ADC ; Initialize the AtoD Converter
;*********************************************************************************
bic.b #CS,&P3OUT ; Set ADC /CS Lo
mov.b #WRITE,&U0TXBUF ; Write 0xA0h to SPI (generates SCLK)
call #CLEAR ; Clear SPI TX/RX Flag
mov.b #DUMMY,&U0TXBUF ; Dummy write to SPI (generates SCLK)
call #CLEAR
bis.b #CS,&P3OUT ; Set ADC /CS Hi
bic.b #CS,&P3OUT ; Set ADC /CS Lo
; Configuration Write to ADC
; See "TLC357X.h" file for details on the following parameters
mov.b #(WRITE+SHORT_SAMP+EXT_REF),&U0TXBUF
call #CLEAR
mov.b #DUMMY,&U0TXBUF ; Dummy write to SPI (generates SCLK)
call #CLEAR
bis.b #CS,&P3OUT ; Set ADC /CS Hi
ret
;*********************************************************************************
IRQ_ISR; Exit LPM0 on reti
;*********************************************************************************
bic.b #01h, &P1OUT
bis.b #CS, &P3OUT ; Set ADC /CS High
bic.b #02h, &P1IFG
reti ; return from interrupt
;*********************************************************************************
COMMON INTVEC ; MSP430x11x1/MSP430F14x Interrupt vectors
;*********************************************************************************
ORG RESET_VECTOR
RESET_VEC DW RESET_ISR ; POR, ext. Reset, Watchdog
ORG PORT1_VECTOR
PORT1_VEC DW IRQ_ISR ; PORT1, Ext. Int.
END
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