📄 main.lis
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0002 ; #define nRF24L01_CE BIT7
0002 ; #define nRF24L01_MISO BIT3
0002 ; #define nRF24L01_IRQ BIT2
0002 ; #define nRF24L01_CSNH SETBIT(PORTD, BIT6)
0002 ; #define nRF24L01_CSNL CLEARBIT(PORTD, BIT6)
0002 ;
0002 ; #define nRF24L01_SCKH SETBIT(PORTB,BIT1)
0002 ; #define nRF24L01_SCKL CLEARBIT(PORTB,BIT1)
0002 ;
0002 ; #define nRF24L01_MOSIH SETBIT(PORTB,BIT0)
0002 ; #define nRF24L01_MOSIL CLEARBIT(PORTB,BIT0)
0002 ;
0002 ; #define nRF24L01_CEH SETBIT(PORTD,BIT7)
0002 ; #define nRF24L01_CEL CLEARBIT(PORTD,BIT7)
0002 ; //-----------------------------------------------------------------------------
0002 ; void main(void)
0002 ; {
0002 .dbline 128
0002 ; unsigned char Get_SO=0;
0002 AA24 clr R10
0004 .dbline 129
0004 ; CLI(); /* global interrupt disable */
0004 F894 cli
0006 .dbline 130
0006 ; init_CPU ();
0006 76D0 rcall _init_CPU
0008 .dbline 131
0008 ; delayms(100); //延时10ms*10=100ms
0008 04E6 ldi R16,100
000A 10E0 ldi R17,0
000C 9BD0 rcall _delayms
000E .dbline 132
000E ; delayms(100); //延时10ms*10=100ms
000E 04E6 ldi R16,100
0010 10E0 ldi R17,0
0012 98D0 rcall _delayms
0014 .dbline 133
0014 ; RX_Mode();
0014 0DD1 rcall _RX_Mode
0016 6BC0 rjmp L3
0018 L2:
0018 .dbline 135
0018 ; while(1)
0018 ; {
0018 .dbline 137
0018 ; // if(!(PINB& 0x01))
0018 ; if(!(PINB& 0x04))
0018 1A99 sbic 0x3,2
001A 29C0 rjmp L5
001C X0:
001C .dbline 138
001C ; {//nRF24L01 接收数据
001C .dbline 139
001C ; key_debug=SPI_Read(STATUS); // read register STATUS's value
001C 07E0 ldi R16,7
001E C8D0 rcall _SPI_Read
0020 00930000 sts _key_debug,R16
0024 .dbline 140
0024 ; if(key_debug&RX_DR) // if renRF24L01_CEive data ready (RX_DR) interrupt
0024 06FF sbrs R16,6
0026 06C0 rjmp L7
0028 X1:
0028 .dbline 141
0028 ; SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
0028 84E1 ldi R24,20
002A 8883 std y+0,R24
002C 20E0 ldi R18,<_Buffer
002E 30E0 ldi R19,>_Buffer
0030 01E6 ldi R16,97
0032 CED0 rcall _SPI_Read_Buf
0034 L7:
0034 .dbline 142
0034 ; if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
0034 20900000 lds R2,_key_debug
0038 24FE sbrs R2,4
003A 03C0 rjmp L9
003C X2:
003C .dbline 142
003C 2227 clr R18
003E 01EE ldi R16,225
0040 A9D0 rcall _SPI_RW_Reg
0042 L9:
0042 .dbline 143
0042 ; SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
0042 2FEF ldi R18,255
0044 07E2 ldi R16,39
0046 A6D0 rcall _SPI_RW_Reg
0048 .dbline 144
0048 ; RX_Mode();
0048 F3D0 rcall _RX_Mode
004A .dbline 145
004A ; if((Buffer[0]==80)&&(Buffer[1]==01))//data accept
004A 80910000 lds R24,_Buffer
004E 8035 cpi R24,80
0050 71F4 brne L11
0052 X3:
0052 80910100 lds R24,_Buffer+1
0056 8130 cpi R24,1
0058 51F4 brne L11
005A X4:
005A .dbline 146
005A ; {
005A .dbline 147
005A ; accept_flag=1;
005A 81E0 ldi R24,1
005C 80934500 sts _accept_flag,R24
0060 .dbline 148
0060 ; PORTC = 0x02;
0060 82E0 ldi R24,2
0062 88B9 out 0x8,R24
0064 .dbline 149
0064 ; delayms(5000); //延时10ms*10=100ms
0064 08E8 ldi R16,5000
0066 13E1 ldi R17,19
0068 6DD0 rcall _delayms
006A .dbline 150
006A ; PORTC = 0x00;
006A 2224 clr R2
006C 28B8 out 0x8,R2
006E .dbline 151
006E ; }
006E L11:
006E .dbline 152
006E ; }
006E L5:
006E .dbline 153
006E ; if(accept_flag==0)//data send
006E 20904500 lds R2,_accept_flag
0072 2220 tst R2
0074 D1F4 brne L14
0076 X5:
0076 .dbline 154
0076 ; {
0076 .dbline 155
0076 ; accept_flag=1;
0076 81E0 ldi R24,1
0078 80934500 sts _accept_flag,R24
007C .dbline 156
007C ; accept_time=0;
007C 2224 clr R2
007E 3324 clr R3
0080 30924700 sts _accept_time+1,R3
0084 20924600 sts _accept_time,R2
0088 .dbline 157
0088 ; Buffer[0]=80;
0088 80E5 ldi R24,80
008A 80930000 sts _Buffer,R24
008E .dbline 158
008E ; Buffer[1]=02;
008E 82E0 ldi R24,2
0090 80930100 sts _Buffer+1,R24
0094 .dbline 159
0094 ; TX_Mode(); // set TX Mode and transmitting
0094 ECD0 rcall _TX_Mode
0096 .dbline 160
0096 ; Buffer[0]=80;
0096 80E5 ldi R24,80
0098 80930000 sts _Buffer,R24
009C .dbline 161
009C ; Buffer[1]=02;
009C 82E0 ldi R24,2
009E 80930100 sts _Buffer+1,R24
00A2 .dbline 162
00A2 ; TX_Mode(); // set TX Mode and transmitting
00A2 E5D0 rcall _TX_Mode
00A4 .dbline 163
00A4 ; delayms(100);
00A4 04E6 ldi R16,100
00A6 10E0 ldi R17,0
00A8 4DD0 rcall _delayms
00AA .dbline 164
00AA ; }
00AA L14:
00AA .dbline 165
00AA ; if(accept_flag=1)
00AA 81E0 ldi R24,1
00AC 80934500 sts _accept_flag,R24
00B0 8823 tst R24
00B2 E9F0 breq L18
00B4 X6:
00B4 .dbline 166
00B4 ; {
00B4 .dbline 167
00B4 ; accept_time++;
00B4 80914600 lds R24,_accept_time
00B8 90914700 lds R25,_accept_time+1
00BC 0196 adiw R24,1
00BE 90934700 sts _accept_time+1,R25
00C2 80934600 sts _accept_time,R24
00C6 .dbline 168
00C6 ; delayms(100);
00C6 04E6 ldi R16,100
00C8 10E0 ldi R17,0
00CA 3CD0 rcall _delayms
00CC .dbline 169
00CC ; if(accept_time>1000)
00CC 88EE ldi R24,1000
00CE 93E0 ldi R25,3
00D0 20904600 lds R2,_accept_time
00D4 30904700 lds R3,_accept_time+1
00D8 8215 cp R24,R2
00DA 9305 cpc R25,R3
00DC 40F4 brsh L20
00DE X7:
00DE .dbline 170
00DE ; {
00DE .dbline 171
00DE ; accept_flag=0;
00DE 2224 clr R2
00E0 20924500 sts _accept_flag,R2
00E4 .dbline 172
00E4 ; accept_time=0;
00E4 3324 clr R3
00E6 30924700 sts _accept_time+1,R3
00EA 20924600 sts _accept_time,R2
00EE .dbline 173
00EE ; }
00EE L20:
00EE .dbline 174
00EE ; }
00EE L18:
00EE .dbline 175
00EE ; }
00EE L3:
00EE .dbline 134
00EE 94CF rjmp L2
00F0 X8:
00F0 .dbline -2
00F0 L1:
00F0 .dbline 0 ; func end
00F0 2196 adiw R28,1
00F2 0895 ret
00F4 .dbsym r Get_SO 10 c
00F4 .dbend
00F4 .dbfunc e init_CPU _init_CPU fV
.even
00F4 _init_CPU::
00F4 .dbline -1
00F4 .dbline 184
00F4 ;
00F4 ;
00F4 ; }
00F4 ; /*-----------------------------------------------------------------------------
00F4 ; Module: init_CPU
00F4 ; Function: Initialization of CPU
00F4 ; ------------------------------------------------------------------------------*/
00F4 ; void init_CPU (void)
00F4 ; {
00F4 .dbline 185
00F4 ; MCUCR = 0x00; //
00F4 2224 clr R2
00F6 25BE out 0x35,R2
00F8 .dbline 186
00F8 ; EICRA = 0x00; //extended ext ints
00F8 20926900 sts 105,R2
00FC .dbline 187
00FC ; EIMSK = 0x00;
00FC 2DBA out 0x1d,R2
00FE .dbline 189
00FE ;
00FE ; TIMSK0 = 0x01; //timer 0 interrupt sources
00FE 81E0 ldi R24,1
0100 80936E00 sts 110,R24
0104 .dbline 190
0104 ; TIMSK1 = 0x00; //timer 1 interrupt sources
0104 20926F00 sts 111,R2
0108 .dbline 191
0108 ; TIMSK2 = 0x00; //timer 2 interrupt sources
0108 20927000 sts 112,R2
010C .dbline 192
010C ; CLI(); //disable all interrupts
010C F894 cli
010E .dbline 193
010E ; NOP();
010E 0000 nop
0110 .dbline 194
0110 ; PORTB = 0x81;
0110 81E8 ldi R24,129
0112 85B9 out 0x5,R24
0114 .dbline 195
0114 ; DDRB = 0xf3;
0114 83EF ldi R24,243
0116 84B9 out 0x4,R24
0118 .dbline 196
0118 ; PORTD = 0x80;
0118 80E8 ldi R24,128
011A 8BB9 out 0xb,R24
011C .dbline 197
011C ; DDRD = 0xff;
011C 8FEF ldi R24,255
011E 8AB9 out 0xa,R24
0120 .dbline 198
0120 ; PORTC = 0x80;
0120 80E8 ldi R24,128
0122 88B9 out 0x8,R24
0124 .dbline 199
0124 ; DDRC = 0x78;
0124 88E7 ldi R24,120
0126 87B9 out 0x7,R24
0128 .dbline 200
0128 ; nRF24L01_CEL;
0128 5F98 cbi 0xb,7
012A .dbline 201
012A ; delay();
012A 05D0 rcall _delay
012C .dbline 202
012C ; nRF24L01_CSNH; // Spi disable
012C 5E9A sbi 0xb,6
012E .dbline 203
012E ; delay();
012E 03D0 rcall _delay
0130 .dbline 204
0130 ; nRF24L01_SCKL;
0130 2998 cbi 0x5,1
0132 .dbline 205
0132 ; delay();
0132 01D0 rcall _delay
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