📄 main.s
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.module main.c
.area text(rom, con, rel)
.dbfile E:\acceptavrnrf24l01\main.c
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.dbsym e Buffer _Buffer A[64:64]c
_TX_ADDRESS::
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.dbsym e TX_ADDRESS _TX_ADDRESS A[5:5]c
_accept_flag::
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.dbfile E:\acceptavrnrf24l01\main.c
.dbsym e accept_flag _accept_flag c
_accept_time::
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.word 0
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.dbfile E:\acceptavrnrf24l01\main.c
.dbsym e accept_time _accept_time i
.area text(rom, con, rel)
.dbfile E:\acceptavrnrf24l01\main.c
.dbfunc e main _main fV
; Get_SO -> R10
.even
_main::
sbiw R28,1
.dbline -1
.dbline 127
; //ICC-AVR application builder : 2006-02-12 14:00:00
; // Target : ATmega48
; // Crystal: 8.000Mhz
; // Author: jackyan
; // Oled Type : white
; //#define fosc 8000000
; //#define baud 9600
; #include "iom48v.h"
; #include "macros.h"
; #include "defs.h"
; /*-----------------------------------------------------------------------------
; Global Defines
; ------------------------------------------------------------------------------*/
; unsigned char key_debug;
; unsigned char Buffer[]={
; 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
; 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
; 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
; 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
; };
; #define TX_ADR_WIDTH 5 // 5 bytes TX(RX) address width
; #define TX_PLOAD_WIDTH 20 // 16 bytes TX payload
; unsigned char TX_ADDRESS[TX_ADR_WIDTH] = {0x34,0x43,0x10,0x10,0x01}; // Define a static TX address
; void init_CPU (void);
; void delayms(unsigned short dly);//当dly=1时，延时的时间是1ms 4MHz晶震
; void INIT_io(void);
; void RX_Mode(void);
; void TX_Mode(void);
; void delay(void);
; unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
; unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
; unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value);
; unsigned char SPI_Read(unsigned char reg);
; void clear_buf(unsigned char *ptr,unsigned char number);
; unsigned char accept_flag=0;
; unsigned int accept_time=0;
; //****************************************************************//
; // SPI(nRF24L01) commands
; #define READ_REG 0x00 // Define read command to register
; #define WRITE_REG 0x20 // Define write command to register
; #define RD_RX_PLOAD 0x61 // Define RX payload register address
; #define WR_TX_PLOAD 0xA0 // Define TX payload register address
; #define FLUSH_TX 0xE1 // Define flush TX register command
; #define FLUSH_RX 0xE2 // Define flush RX register command
; #define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
; //#define NOP 0xFF // Define No Operation, might be used to read status register
; //***************************************************//
; // SPI(nRF24L01) registers(addresses)
; #define CONFIG 0x00 // 'Config' register address
; #define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
; #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
; #define SETUP_AW 0x03 // 'Setup address width' register address
; #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
; #define RF_CH 0x05 // 'RF channel' register address
; #define RF_SETUP 0x06 // 'RF setup' register address
; #define STATUS 0x07 // 'Status' register address
; #define OBSERVE_TX 0x08 // 'Observe TX' register address
; #define CD 0x09 // 'Carrier Detect' register address
; #define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
; #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
; #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
; #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
; #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
; #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
; #define TX_ADDR 0x10 // 'TX address' register address
; #define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
; #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
; #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
; #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
; #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
; #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
; #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
; #define MAX_RT 0x10 // Max #of TX retrans interrupt
; #define TX_DS 0x20 // TX data sent interrupt
; #define RX_DR 0x40 // RX data received
; //-----------------------------------------------------------------------------
; //------------------------------------------------------
; #define BIT(x) (1 << (x))
; #define SETBIT(x, y) (x |= y)
; #define CLEARBIT(x, y) (x &= ~y)
; #define CHECKBIT(x, y) (x & y)
; #define BIT7 0x80
; #define BIT6 0x40
; #define BIT5 0x20
; #define BIT4 0x10
; #define BIT3 0x08
; #define BIT2 0x04
; #define BIT1 0x02
; #define BIT0 0x01
; /*#define nRF24L01_CSN BIT4
; #define nRF24L01_SCK BIT5
; #define nRF24L01_MOSI BIT6
; #define nRF24L01_CE BIT3
; #define nRF24L01_MISO BIT7
; #define nRF24L01_IRQ BIT0
; #define nRF24L01_CSNH SETBIT(PORTD, BIT4)
; #define nRF24L01_CSNL CLEARBIT(PORTD, BIT4)
;
; #define nRF24L01_SCKH SETBIT(PORTD,BIT5)
; #define nRF24L01_SCKL CLEARBIT(PORTD,BIT5)
;
; #define nRF24L01_MOSIH SETBIT(PORTD,BIT6)
; #define nRF24L01_MOSIL CLEARBIT(PORTD,BIT6)
;
; #define nRF24L01_CEH SETBIT(PORTD,BIT3)
; #define nRF24L01_CEL CLEARBIT(PORTD,BIT3) */
; //-----------------------------------------------------------------------------
; #define nRF24L01_CSN BIT6
; #define nRF24L01_SCK BIT1
; #define nRF24L01_MOSI BIT0
; #define nRF24L01_CE BIT7
; #define nRF24L01_MISO BIT3
; #define nRF24L01_IRQ BIT2
; #define nRF24L01_CSNH SETBIT(PORTD, BIT6)
; #define nRF24L01_CSNL CLEARBIT(PORTD, BIT6)
;
; #define nRF24L01_SCKH SETBIT(PORTB,BIT1)
; #define nRF24L01_SCKL CLEARBIT(PORTB,BIT1)
;
; #define nRF24L01_MOSIH SETBIT(PORTB,BIT0)
; #define nRF24L01_MOSIL CLEARBIT(PORTB,BIT0)
;
; #define nRF24L01_CEH SETBIT(PORTD,BIT7)
; #define nRF24L01_CEL CLEARBIT(PORTD,BIT7)
; //-----------------------------------------------------------------------------
; void main(void)
; {
.dbline 128
; unsigned char Get_SO=0;
clr R10
.dbline 129
; CLI(); /* global interrupt disable */
cli
.dbline 130
; init_CPU ();
rcall _init_CPU
.dbline 131
; delayms(100); //延时10ms*10=100ms
ldi R16,100
ldi R17,0
rcall _delayms
.dbline 132
; delayms(100); //延时10ms*10=100ms
ldi R16,100
ldi R17,0
rcall _delayms
.dbline 133
; RX_Mode();
rcall _RX_Mode
rjmp L3
L2:
.dbline 135
; while(1)
; {
.dbline 137
; // if(!(PINB& 0x01))
; if(!(PINB& 0x04))
sbic 0x3,2
rjmp L5
X0:
.dbline 138
; {//nRF24L01 接收数据
.dbline 139
; key_debug=SPI_Read(STATUS); // read register STATUS's value
ldi R16,7
rcall _SPI_Read
sts _key_debug,R16
.dbline 140
; if(key_debug&RX_DR) // if renRF24L01_CEive data ready (RX_DR) interrupt
sbrs R16,6
rjmp L7
X1:
.dbline 141
; SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
ldi R24,20
std y+0,R24
ldi R18,<_Buffer
ldi R19,>_Buffer
ldi R16,97
rcall _SPI_Read_Buf
L7:
.dbline 142
; if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
lds R2,_key_debug
sbrs R2,4
rjmp L9
X2:
.dbline 142
clr R18
ldi R16,225
rcall _SPI_RW_Reg
L9:
.dbline 143
; SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
ldi R18,255
ldi R16,39
rcall _SPI_RW_Reg
.dbline 144
; RX_Mode();
rcall _RX_Mode
.dbline 145
; if((Buffer[0]==80)&&(Buffer[1]==02))//data accept
lds R24,_Buffer
cpi R24,80
brne L11
X3:
lds R24,_Buffer+1
cpi R24,2
brne L11
X4:
.dbline 146
; {
.dbline 147
; accept_flag=1;
ldi R24,1
sts _accept_flag,R24
.dbline 148
; PORTC = 0x02;
ldi R24,2
out 0x8,R24
.dbline 149
; delayms(5000); //延时10ms*10=100ms
ldi R16,5000
ldi R17,19
rcall _delayms
.dbline 150
; PORTC = 0x00;
clr R2
out 0x8,R2
.dbline 151
; }
L11:
.dbline 152
; }
L5:
.dbline 153
; if(accept_flag==0)//data send
lds R2,_accept_flag
tst R2
brne L14
X5:
.dbline 154
; {
.dbline 155
; accept_flag=1;
ldi R24,1
sts _accept_flag,R24
.dbline 156
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