📄 oled.lst
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C8 E180 LDI R24,0x10
C9 E297 LDI R25,0x27
CA 9020 0146 LDS R2,accept_time
CC 9030 0147 LDS R3,accept_time+1
CE 1582 CP R24,R2
CF 0593 CPC R25,R3
D0 F440 BCC 0x00D9
(0173) {
(0174) accept_flag=0;
D1 2422 CLR R2
D2 9220 0145 STS accept_flag,R2
(0175) accept_time=0;
D4 2433 CLR R3
D5 9230 0147 STS accept_time+1,R3
D7 9220 0146 STS accept_time,R2
(0176) }
(0177) //-------------------------------------------
(0178) // if(!(PINB& 0x01))
(0179) if(!(PINB& 0x04))
D9 991A SBIC 0x03,2
DA C02C RJMP 0x0107
(0180) {//nRF24L01 接收数据
(0181) key_debug=SPI_Read(STATUS); // read register STATUS's value
DB E007 LDI R16,7
DC D08B RCALL _SPI_Read
DD 9300 0148 STS key_debug,R16
(0182) if(key_debug&RX_DR) // if renRF24L01_CEive data ready (RX_DR) interrupt
DF FF06 SBRS R16,6
E0 C006 RJMP 0x00E7
(0183) SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
E1 E184 LDI R24,0x14
E2 8388 STD Y+0,R24
E3 E020 LDI R18,0
E4 E031 LDI R19,1
E5 E601 LDI R16,0x61
E6 D091 RCALL _SPI_Read_Buf
(0184) if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
E7 9020 0148 LDS R2,key_debug
E9 FE24 SBRS R2,4
EA C003 RJMP 0x00EE
EB 2722 CLR R18
EC EE01 LDI R16,0xE1
ED D06C RCALL _SPI_RW_Reg
(0185) SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
EE EF2F LDI R18,0xFF
EF E207 LDI R16,0x27
F0 D069 RCALL _SPI_RW_Reg
(0186) RX_Mode();
F1 D0B6 RCALL _RX_Mode
(0187) if((Buffer[0]==80)&&(Buffer[1]==02))//data accept
F2 9180 0100 LDS R24,Buffer
F4 3580 CPI R24,0x50
F5 F489 BNE 0x0107
F6 9180 0101 LDS R24,Buffer+1
F8 3082 CPI R24,2
F9 F469 BNE 0x0107
(0188) {
(0189) accept_flag=1;
FA E081 LDI R24,1
FB 9380 0145 STS accept_flag,R24
(0190) PORTC = 0x02;
FD E082 LDI R24,2
FE B988 OUT 0x08,R24
(0191) delayms(5000); //延时10ms*10=100ms
FF E808 LDI R16,0x88
100 E113 LDI R17,0x13
101 D030 RCALL _delayms
(0192) delayms(5000); //延时10ms*10=100ms
102 E808 LDI R16,0x88
103 E113 LDI R17,0x13
104 D02D RCALL _delayms
(0193) PORTC = 0x00;
105 2422 CLR R2
106 B828 OUT 0x08,R2
107 CF62 RJMP 0x006A
108 9621 ADIW R28,1
109 9508 RET
(0194) }
(0195) }
(0196) //-------------------------------------------
(0197) }
(0198) }
(0199)
(0200)
(0201) }
(0202) /*-----------------------------------------------------------------------------
(0203) Module: init_CPU
(0204) Function: Initialization of CPU
(0205) ------------------------------------------------------------------------------*/
(0206) void init_CPU (void)
(0207) {
(0208) MCUCR = 0x00; //
_init_CPU:
10A 2422 CLR R2
10B BE25 OUT 0x35,R2
(0209) EICRA = 0x00; //extended ext ints
10C 9220 0069 STS 0x0069,R2
(0210) EIMSK = 0x00;
10E BA2D OUT 0x1D,R2
(0211)
(0212) TIMSK0 = 0x01; //timer 0 interrupt sources
10F E081 LDI R24,1
110 9380 006E STS 0x006E,R24
(0213) TIMSK1 = 0x00; //timer 1 interrupt sources
112 9220 006F STS 0x006F,R2
(0214) TIMSK2 = 0x00; //timer 2 interrupt sources
114 9220 0070 STS 0x0070,R2
(0215) CLI(); //disable all interrupts
116 94F8 BCLR 7
(0216) NOP();
117 0000 NOP
(0217) PORTB = 0x81;
118 E881 LDI R24,0x81
119 B985 OUT 0x05,R24
(0218) DDRB = 0xf3;
11A EF83 LDI R24,0xF3
11B B984 OUT 0x04,R24
(0219) PORTD = 0x80;
11C E880 LDI R24,0x80
11D B98B OUT 0x0B,R24
(0220) DDRD = 0xff;
11E EF8F LDI R24,0xFF
11F B98A OUT 0x0A,R24
(0221) PORTC = 0x80;
120 E880 LDI R24,0x80
121 B988 OUT 0x08,R24
(0222) DDRC = 0x78;
122 E788 LDI R24,0x78
123 B987 OUT 0x07,R24
(0223) nRF24L01_CEL;
124 985F CBI 0x0B,7
(0224) delay();
125 D005 RCALL _delay
(0225) nRF24L01_CSNH; // Spi disable
126 9A5E SBI 0x0B,6
(0226) delay();
127 D003 RCALL _delay
(0227) nRF24L01_SCKL;
128 9829 CBI 0x05,1
(0228) delay();
129 D001 RCALL _delay
12A 9508 RET
(0229) }
(0230) void delay(void)//
(0231) {
(0232) NOP();
_delay:
12B 0000 NOP
(0233) NOP();
12C 0000 NOP
(0234) NOP();
12D 0000 NOP
(0235) NOP();
12E 0000 NOP
(0236) NOP();
12F 0000 NOP
(0237) NOP();
130 0000 NOP
131 9508 RET
(0238) }
(0239) void delayms(unsigned short dly)//
(0240) {
(0241) for(;dly>0;dly--) ;
_delayms:
dly --> R16
132 C002 RJMP 0x0135
133 5001 SUBI R16,1
134 4010 SBCI R17,0
135 3000 CPI R16,0
136 0701 CPC R16,R17
137 F7D9 BNE 0x0133
138 9508 RET
(0242) }
(0243)
(0244) void clear_buf(unsigned char *ptr,unsigned char number)//清零buffer,指定字节个数
(0245) {
(0246) for (;number>0;number--) *ptr++=0;
_clear_buf:
number --> R18
ptr --> R16
139 C005 RJMP 0x013F
13A 2422 CLR R2
13B 01F8 MOVW R30,R16
13C 9221 ST R2,Z+
13D 018F MOVW R16,R30
13E 952A DEC R18
13F E080 LDI R24,0
140 1782 CP R24,R18
141 F3C0 BCS 0x013A
142 9508 RET
_SPI_RW:
bit_ctr --> R22
byte --> R20
143 D0C5 RCALL push_xgsetF000
144 2F40 MOV R20,R16
(0247) }
(0248) //------------------------------------------------------
(0249) /**************************************************
(0250) Function: SPI_RW();
(0251)
(0252) Description:
(0253) Writes one byte to nRF24L01, and return the byte read
(0254) from nRF24L01 during write, according to SPI protocol */
(0255) /**************************************************/
(0256) unsigned char SPI_RW(unsigned char byte)
(0257) {
(0258) unsigned char bit_ctr;
(0259) for(bit_ctr=0;bit_ctr<8;bit_ctr++) // output 8-bit
145 2766 CLR R22
146 C00F RJMP 0x0156
(0260) {
(0261) if(byte & 0x80)
147 FF47 SBRS R20,7
148 C002 RJMP 0x014B
(0262) nRF24L01_MOSIH;
149 9A28 SBI 0x05,0
14A C001 RJMP 0x014C
(0263) else
(0264) nRF24L01_MOSIL;
14B 9828 CBI 0x05,0
(0265) delay();
14C DFDE RCALL _delay
(0266) byte = (byte << 1); // shift next bit into MSB..
14D 0F44 LSL R20
(0267) nRF24L01_SCKH;
14E 9A29 SBI 0x05,1
(0268) delay();
14F DFDB RCALL _delay
(0269) if(PINB&0x08) byte |= 1;
150 9B1B SBIS 0x03,3
151 C001 RJMP 0x0153
152 6041 ORI R20,1
(0270) nRF24L01_SCKL;
153 9829 CBI 0x05,1
(0271) delay();
154 DFD6 RCALL _delay
155 9563 INC R22
156 3068 CPI R22,0x8
157 F378 BCS 0x0147
(0272) }
(0273) return(byte); // return read byte
158 2F04 MOV R16,R20
159 C0B4 RJMP pop_xgsetF000
_SPI_RW_Reg:
status --> R10
value --> R12
reg --> R10
15A D0A9 RCALL push_xgset003C
15B 2EC2 MOV R12,R18
15C 2EA0 MOV R10,R16
(0274) }
(0275) /**************************************************
(0276) Function: SPI_RW_Reg();
(0277)
(0278) Description:
(0279) Writes value 'value' to register 'reg' */
(0280) /**************************************************/
(0281) unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value)
(0282) {
(0283) unsigned char status;
(0284) nRF24L01_CSNL;
15D 985E CBI 0x0B,6
(0285) delay();
15E DFCC RCALL _delay
(0286) status = SPI_RW(reg); // select register
15F 2D0A MOV R16,R10
160 DFE2 RCALL _SPI_RW
161 2EA0 MOV R10,R16
(0287) SPI_RW(value); // ..and write value to it..
162 2D0C MOV R16,R12
163 DFDF RCALL _SPI_RW
(0288) nRF24L01_CSNH;
164 9A5E SBI 0x0B,6
(0289) delay();
165 DFC5 RCALL _delay
(0290) return(status); // return nRF24L01 status byte
166 2D0A MOV R16,R10
167 C08A RJMP pop_xgset003C
_SPI_Read:
reg_val --> R10
reg --> R10
168 92AA ST R10,-Y
169 92BA ST R11,-Y
16A 2EA0 MOV R10,R16
(0291) }
(0292) /**************************************************
(0293) Function: SPI_Read();
(0294)
(0295) Description:
(0296) Read one byte from nRF24L01 register, 'reg' */
(0297) /**************************************************/
(0298) unsigned char SPI_Read(unsigned char reg)
(0299) {
(0300) unsigned char reg_val;
(0301) nRF24L01_CSNL;
16B 985E CBI 0x0B,6
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