📄 main.lis
字号:
0232 0895 ret
0234 .dbsym r reg_val 10 c
0234 .dbsym r reg 10 c
0234 .dbend
0234 .dbfunc e SPI_Read_Buf _SPI_Read_Buf fc
0234 ; status -> R10
0234 ; byte_ctr -> R12
0234 ; bytes -> y+6
0234 ; pBuf -> R14,R15
0234 ; reg -> R10
.even
0234 _SPI_Read_Buf::
0234 00D0 rcall push_xgset00FC
0236 7901 movw R14,R18
0238 A02E mov R10,R16
023A .dbline -1
023A .dbline 317
023A ; }
023A ; /**************************************************
023A ; Function: SPI_Read_Buf();
023A ;
023A ; Description:
023A ; Reads 'bytes' #of bytes from register 'reg'
023A ; Typically used to read RX payload, Rx/Tx address */
023A ; /**************************************************/
023A ; unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes)
023A ; {
023A .dbline 319
023A ; unsigned char status,byte_ctr;
023A ; nRF24L01_CSNL;
023A 5E98 cbi 0xb,6
023C .dbline 320
023C ; delay();
023C AEDF rcall _delay
023E .dbline 321
023E ; status = SPI_RW(reg); // Select register to write to and read status byte
023E 0A2D mov R16,R10
0240 C4DF rcall _SPI_RW
0242 A02E mov R10,R16
0244 .dbline 322
0244 ; for(byte_ctr=0;byte_ctr<bytes;byte_ctr++)
0244 CC24 clr R12
0246 08C0 rjmp L59
0248 L56:
0248 .dbline 323
0248 ; pBuf[byte_ctr] = SPI_RW(0); // Perform SPI_RW to read byte from nRF24L01
0248 0027 clr R16
024A BFDF rcall _SPI_RW
024C EC2D mov R30,R12
024E FF27 clr R31
0250 EE0D add R30,R14
0252 FF1D adc R31,R15
0254 0083 std z+0,R16
0256 L57:
0256 .dbline 322
0256 C394 inc R12
0258 L59:
0258 .dbline 322
0258 0E80 ldd R0,y+6
025A C014 cp R12,R0
025C A8F3 brlo L56
025E X20:
025E .dbline 324
025E ; nRF24L01_CSNH;
025E 5E9A sbi 0xb,6
0260 .dbline 325
0260 ; delay();
0260 9CDF rcall _delay
0262 .dbline 326
0262 ; return(status); // return nRF24L01 status byte
0262 0A2D mov R16,R10
0264 .dbline -2
0264 L55:
0264 .dbline 0 ; func end
0264 00C0 rjmp pop_xgset00FC
0266 .dbsym r status 10 c
0266 .dbsym r byte_ctr 12 c
0266 .dbsym l bytes 6 c
0266 .dbsym r pBuf 14 pc
0266 .dbsym r reg 10 c
0266 .dbend
0266 .dbfunc e SPI_Write_Buf _SPI_Write_Buf fc
0266 ; status -> R10
0266 ; byte_ctr -> R12
0266 ; bytes -> y+6
0266 ; pBuf -> R14,R15
0266 ; reg -> R10
.even
0266 _SPI_Write_Buf::
0266 00D0 rcall push_xgset00FC
0268 7901 movw R14,R18
026A A02E mov R10,R16
026C .dbline -1
026C .dbline 336
026C ; }
026C ; /**************************************************
026C ; Function: SPI_Write_Buf();
026C ;
026C ; Description:
026C ; Writes contents of buffer '*pBuf' to nRF24L01
026C ; Typically used to write TX payload, Rx/Tx address */
026C ; /**************************************************/
026C ; unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes)
026C ; {
026C .dbline 338
026C ; unsigned char status,byte_ctr;
026C ; nRF24L01_CSNL; // Set nRF24L01_CSN low, init SPI tranaction
026C 5E98 cbi 0xb,6
026E .dbline 339
026E ; delay();
026E 95DF rcall _delay
0270 .dbline 340
0270 ; status = SPI_RW(reg); // Select register to write to and read status byte
0270 0A2D mov R16,R10
0272 ABDF rcall _SPI_RW
0274 A02E mov R10,R16
0276 .dbline 341
0276 ; for(byte_ctr=0; byte_ctr<bytes; byte_ctr++) // then write all byte in buffer(*pBuf)
0276 CC24 clr R12
0278 06C0 rjmp L64
027A L61:
027A .dbline 342
027A ; status = SPI_RW(*pBuf++);
027A F701 movw R30,R14
027C 0191 ld R16,Z+
027E 7F01 movw R14,R30
0280 A4DF rcall _SPI_RW
0282 A02E mov R10,R16
0284 L62:
0284 .dbline 341
0284 C394 inc R12
0286 L64:
0286 .dbline 341
0286 0E80 ldd R0,y+6
0288 C014 cp R12,R0
028A B8F3 brlo L61
028C X21:
028C .dbline 343
028C ; nRF24L01_CSNH; // Set nRF24L01_CSN high again
028C 5E9A sbi 0xb,6
028E .dbline 344
028E ; delay();
028E 85DF rcall _delay
0290 .dbline 345
0290 ; return(status); // return nRF24L01 status byte
0290 0A2D mov R16,R10
0292 .dbline -2
0292 L60:
0292 .dbline 0 ; func end
0292 00C0 rjmp pop_xgset00FC
0294 .dbsym r status 10 c
0294 .dbsym r byte_ctr 12 c
0294 .dbsym l bytes 6 c
0294 .dbsym r pBuf 14 pc
0294 .dbsym r reg 10 c
0294 .dbend
0294 .dbfunc e RX_Mode _RX_Mode fV
.even
0294 _RX_Mode::
0294 2197 sbiw R28,1
0296 .dbline -1
0296 .dbline 358
0296 ; }
0296 ; /**************************************************
0296 ; Function: RX_Mode();
0296 ;
0296 ; Description:
0296 ; This function initializes one nRF24L01 device to
0296 ; RX Mode, set RX address, writes RX payload width,
0296 ; select RF channel, datarate & LNA HCURR.
0296 ; After init, CE is toggled high, which means that
0296 ; this device is now ready to receive a datapacket. */
0296 ; /**************************************************/
0296 ; void RX_Mode(void)
0296 ; {
0296 .dbline 359
0296 ; nRF24L01_CEL;
0296 5F98 cbi 0xb,7
0298 .dbline 360
0298 ; delay();
0298 80DF rcall _delay
029A .dbline 361
029A ; SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // Use the same address on the RX device as the TX device
029A 85E0 ldi R24,5
029C 8883 std y+0,R24
029E 20E0 ldi R18,<_TX_ADDRESS
02A0 30E0 ldi R19,>_TX_ADDRESS
02A2 0AE2 ldi R16,42
02A4 E0DF rcall _SPI_Write_Buf
02A6 .dbline 363
02A6 ;
02A6 ; SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
02A6 21E0 ldi R18,1
02A8 01E2 ldi R16,33
02AA A6DF rcall _SPI_RW_Reg
02AC .dbline 364
02AC ; SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
02AC 21E0 ldi R18,1
02AE 02E2 ldi R16,34
02B0 A3DF rcall _SPI_RW_Reg
02B2 .dbline 365
02B2 ; SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
02B2 28E2 ldi R18,40
02B4 05E2 ldi R16,37
02B6 A0DF rcall _SPI_RW_Reg
02B8 .dbline 366
02B8 ; SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
02B8 24E1 ldi R18,20
02BA 01E3 ldi R16,49
02BC 9DDF rcall _SPI_RW_Reg
02BE .dbline 367
02BE ; SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
02BE 27E0 ldi R18,7
02C0 06E2 ldi R16,38
02C2 9ADF rcall _SPI_RW_Reg
02C4 .dbline 368
02C4 ; SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..
02C4 2FE0 ldi R18,15
02C6 00E2 ldi R16,32
02C8 97DF rcall _SPI_RW_Reg
02CA .dbline 369
02CA ; nRF24L01_CEH;
02CA 5F9A sbi 0xb,7
02CC .dbline 370
02CC ; delay();
02CC 66DF rcall _delay
02CE .dbline -2
02CE L65:
02CE .dbline 0 ; func end
02CE 2196 adiw R28,1
02D0 0895 ret
02D2 .dbend
02D2 .dbfunc e TX_Mode _TX_Mode fV
.even
02D2 _TX_Mode::
02D2 2197 sbiw R28,1
02D4 .dbline -1
02D4 .dbline 390
02D4 ; // This device is now ready to receive one packet of 16 bytes payload from a TX device sending to address
02D4 ; // '3443101001', with auto acknowledgment, retransmit count of 10, RF channel 40 and datarate = 2Mbps.
02D4 ;
02D4 ; }
02D4 ; /**************************************************/
02D4 ;
02D4 ; /**************************************************
02D4 ; Function: TX_Mode();
02D4 ;
02D4 ; Description:
02D4 ; This function initializes one nRF24L01 device to
02D4 ; TX mode, set TX address, set RX address for auto.ack,
02D4 ; fill TX payload, select RF channel, datarate & TX pwr.
02D4 ; PWR_UP is set, CRC(2 bytes) is enabled, & PRIM:TX.
02D4 ;
02D4 ; ToDo: One high pulse(>10us) on CE will now send this
02D4 ; packet and expext an acknowledgment from the RX device. */
02D4 ; /**************************************************/
02D4 ; void TX_Mode(void)
02D4 ; {
02D4 .dbline 391
02D4 ; nRF24L01_CEL;
02D4 5F98 cbi 0xb,7
02D6 .dbline 392
02D6 ; delay();
02D6 61DF rcall _delay
02D8 .dbline 393
02D8 ; SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // Writes TX_Address to nRF24L01
02D8 85E0 ldi R24,5
02DA 8883 std y+0,R24
02DC 20E0 ldi R18,<_TX_ADDRESS
02DE 30E0 ldi R19,>_TX_ADDRESS
02E0 00E3 ldi R16,48
02E2 C1DF rcall _SPI_Write_Buf
02E4 .dbline 394
02E4 ; SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // RX_Addr0 same as TX_Adr for Auto.Ack
02E4 85E0 ldi R24,5
02E6 8883 std y+0,R24
02E8 20E0 ldi R18,<_TX_ADDRESS
02EA 30E0 ldi R19,>_TX_ADDRESS
02EC 0AE2 ldi R16,42
02EE BBDF rcall _SPI_Write_Buf
02F0 .dbline 395
02F0 ; SPI_Write_Buf(WR_TX_PLOAD, Buffer, TX_PLOAD_WIDTH); // Writes data to TX payload
02F0 84E1 ldi R24,20
02F2 8883 std y+0,R24
02F4 20E0 ldi R18,<_Buffer
02F6 30E0 ldi R19,>_Buffer
02F8 00EA ldi R16,160
02FA B5DF rcall _SPI_Write_Buf
02FC .dbline 397
02FC ;
02FC ; SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
02FC 21E0 ldi R18,1
02FE 01E2 ldi R16,33
0300 7BDF rcall _SPI_RW_Reg
0302 .dbline 398
0302 ; SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
0302 21E0 ldi R18,1
0304 02E2 ldi R16,34
0306 78DF rcall _SPI_RW_Reg
0308 .dbline 399
0308 ; SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1a); // 500us + 86us, 10 retrans...
0308 2AE1 ldi R18,26
030A 04E2 ldi R16,36
030C 75DF rcall _SPI_RW_Reg
030E .dbline 400
030E ; SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
030E 28E2 ldi R18,40
0310 05E2 ldi R16,37
0312 72DF rcall _SPI_RW_Reg
0314 .dbline 401
0314 ; SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
0314 27E0 ldi R18,7
0316 06E2 ldi R16,38
0318 6FDF rcall _SPI_RW_Reg
031A .dbline 402
031A ; SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_DS enabled..
031A 2EE0 ldi R18,14
031C 00E2 ldi R16,32
031E 6CDF rcall _SPI_RW_Reg
0320 .dbline 403
0320 ; nRF24L01_CEH;
0320 5F9A sbi 0xb,7
0322 .dbline 404
0322 ; delay();
0322 3BDF rcall _delay
0324 .dbline -2
0324 L66:
0324 .dbline 0 ; func end
0324 2196 adiw R28,1
0326 0895 ret
0328 .dbend
.area bss(ram, con, rel)
0000 .dbfile E:\acceptavrnrf24l01\main.c
0000 _key_debug::
0000 .blkb 1
0001 .dbsym e key_debug _key_debug c
0001 ;
0001 ; }
0001 ; //------------------------------------------------------
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -