📄 main.lis
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0006 ; init_CPU ();
0006 A8D0 rcall _init_CPU
0008 .dbline 131
0008 ; delayms(100); //延时10ms*10=100ms
0008 04E6 ldi R16,100
000A 10E0 ldi R17,0
000C CDD0 rcall _delayms
000E .dbline 132
000E ; delayms(100); //延时10ms*10=100ms
000E 04E6 ldi R16,100
0010 10E0 ldi R17,0
0012 CAD0 rcall _delayms
0014 .dbline 133
0014 ; RX_Mode();
0014 3FD1 rcall _RX_Mode
0016 9DC0 rjmp L3
0018 L2:
0018 .dbline 135
0018 ; while(1)
0018 ; {
0018 .dbline 137
0018 ; // if(!(PINB& 0x01))
0018 ; if(!(PINB& 0x04))
0018 1A99 sbic 0x3,2
001A 29C0 rjmp L5
001C X0:
001C .dbline 138
001C ; {//nRF24L01 接收数据
001C .dbline 139
001C ; key_debug=SPI_Read(STATUS); // read register STATUS's value
001C 07E0 ldi R16,7
001E FAD0 rcall _SPI_Read
0020 00930000 sts _key_debug,R16
0024 .dbline 140
0024 ; if(key_debug&RX_DR) // if renRF24L01_CEive data ready (RX_DR) interrupt
0024 06FF sbrs R16,6
0026 06C0 rjmp L7
0028 X1:
0028 .dbline 141
0028 ; SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
0028 84E1 ldi R24,20
002A 8883 std y+0,R24
002C 20E0 ldi R18,<_Buffer
002E 30E0 ldi R19,>_Buffer
0030 01E6 ldi R16,97
0032 00D1 rcall _SPI_Read_Buf
0034 L7:
0034 .dbline 142
0034 ; if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
0034 20900000 lds R2,_key_debug
0038 24FE sbrs R2,4
003A 03C0 rjmp L9
003C X2:
003C .dbline 142
003C 2227 clr R18
003E 01EE ldi R16,225
0040 DBD0 rcall _SPI_RW_Reg
0042 L9:
0042 .dbline 143
0042 ; SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
0042 2FEF ldi R18,255
0044 07E2 ldi R16,39
0046 D8D0 rcall _SPI_RW_Reg
0048 .dbline 144
0048 ; RX_Mode();
0048 25D1 rcall _RX_Mode
004A .dbline 145
004A ; if((Buffer[0]==80)&&(Buffer[1]==02))//data accept
004A 80910000 lds R24,_Buffer
004E 8035 cpi R24,80
0050 71F4 brne L11
0052 X3:
0052 80910100 lds R24,_Buffer+1
0056 8230 cpi R24,2
0058 51F4 brne L11
005A X4:
005A .dbline 146
005A ; {
005A .dbline 147
005A ; accept_flag=1;
005A 81E0 ldi R24,1
005C 80934500 sts _accept_flag,R24
0060 .dbline 148
0060 ; PORTC = 0x02;
0060 82E0 ldi R24,2
0062 88B9 out 0x8,R24
0064 .dbline 149
0064 ; delayms(5000); //延时10ms*10=100ms
0064 08E8 ldi R16,5000
0066 13E1 ldi R17,19
0068 9FD0 rcall _delayms
006A .dbline 150
006A ; PORTC = 0x00;
006A 2224 clr R2
006C 28B8 out 0x8,R2
006E .dbline 151
006E ; }
006E L11:
006E .dbline 152
006E ; }
006E L5:
006E .dbline 153
006E ; if(accept_flag==0)//data send
006E 20904500 lds R2,_accept_flag
0072 2220 tst R2
0074 01F5 brne L14
0076 X5:
0076 .dbline 154
0076 ; {
0076 .dbline 155
0076 ; accept_flag=1;
0076 81E0 ldi R24,1
0078 80934500 sts _accept_flag,R24
007C .dbline 156
007C ; accept_time=0;
007C 2224 clr R2
007E 3324 clr R3
0080 30924700 sts _accept_time+1,R3
0084 20924600 sts _accept_time,R2
0088 .dbline 157
0088 ; Buffer[0]=80;
0088 80E5 ldi R24,80
008A 80930000 sts _Buffer,R24
008E .dbline 158
008E ; Buffer[1]=01;
008E 81E0 ldi R24,1
0090 80930100 sts _Buffer+1,R24
0094 .dbline 159
0094 ; TX_Mode(); // set TX Mode and transmitting
0094 1ED1 rcall _TX_Mode
0096 .dbline 160
0096 ; Buffer[0]=80;
0096 80E5 ldi R24,80
0098 80930000 sts _Buffer,R24
009C .dbline 161
009C ; Buffer[1]=01;
009C 81E0 ldi R24,1
009E 80930100 sts _Buffer+1,R24
00A2 .dbline 162
00A2 ; TX_Mode(); // set TX Mode and transmitting
00A2 17D1 rcall _TX_Mode
00A4 .dbline 163
00A4 ; delayms(100);
00A4 04E6 ldi R16,100
00A6 10E0 ldi R17,0
00A8 7FD0 rcall _delayms
00AA .dbline 164
00AA ; RX_Mode();
00AA F4D0 rcall _RX_Mode
00AC .dbline 165
00AC ; Buffer[0]=00;
00AC 2224 clr R2
00AE 20920000 sts _Buffer,R2
00B2 .dbline 166
00B2 ; Buffer[1]=00;
00B2 20920100 sts _Buffer+1,R2
00B6 .dbline 167
00B6 ; }
00B6 L14:
00B6 .dbline 168
00B6 ; if(accept_flag=1)
00B6 81E0 ldi R24,1
00B8 80934500 sts _accept_flag,R24
00BC 8823 tst R24
00BE 09F4 brne X14
00C0 48C0 rjmp L19
00C2 X14:
00C2 X6:
00C2 .dbline 169
00C2 ; {
00C2 .dbline 170
00C2 ; accept_time++;
00C2 80914600 lds R24,_accept_time
00C6 90914700 lds R25,_accept_time+1
00CA 0196 adiw R24,1
00CC 90934700 sts _accept_time+1,R25
00D0 80934600 sts _accept_time,R24
00D4 .dbline 172
00D4 ; // delayms(100);
00D4 ; if(accept_time>10000)
00D4 80E1 ldi R24,10000
00D6 97E2 ldi R25,39
00D8 20904600 lds R2,_accept_time
00DC 30904700 lds R3,_accept_time+1
00E0 8215 cp R24,R2
00E2 9305 cpc R25,R3
00E4 40F4 brsh L21
00E6 X7:
00E6 .dbline 173
00E6 ; {
00E6 .dbline 174
00E6 ; accept_flag=0;
00E6 2224 clr R2
00E8 20924500 sts _accept_flag,R2
00EC .dbline 175
00EC ; accept_time=0;
00EC 3324 clr R3
00EE 30924700 sts _accept_time+1,R3
00F2 20924600 sts _accept_time,R2
00F6 .dbline 176
00F6 ; }
00F6 L21:
00F6 .dbline 179
00F6 ; //-------------------------------------------
00F6 ; // if(!(PINB& 0x01))
00F6 ; if(!(PINB& 0x04))
00F6 1A99 sbic 0x3,2
00F8 2CC0 rjmp L23
00FA X8:
00FA .dbline 180
00FA ; {//nRF24L01 接收数据
00FA .dbline 181
00FA ; key_debug=SPI_Read(STATUS); // read register STATUS's value
00FA 07E0 ldi R16,7
00FC 8BD0 rcall _SPI_Read
00FE 00930000 sts _key_debug,R16
0102 .dbline 182
0102 ; if(key_debug&RX_DR) // if renRF24L01_CEive data ready (RX_DR) interrupt
0102 06FF sbrs R16,6
0104 06C0 rjmp L25
0106 X9:
0106 .dbline 183
0106 ; SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
0106 84E1 ldi R24,20
0108 8883 std y+0,R24
010A 20E0 ldi R18,<_Buffer
010C 30E0 ldi R19,>_Buffer
010E 01E6 ldi R16,97
0110 91D0 rcall _SPI_Read_Buf
0112 L25:
0112 .dbline 184
0112 ; if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
0112 20900000 lds R2,_key_debug
0116 24FE sbrs R2,4
0118 03C0 rjmp L27
011A X10:
011A .dbline 184
011A 2227 clr R18
011C 01EE ldi R16,225
011E 6CD0 rcall _SPI_RW_Reg
0120 L27:
0120 .dbline 185
0120 ; SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
0120 2FEF ldi R18,255
0122 07E2 ldi R16,39
0124 69D0 rcall _SPI_RW_Reg
0126 .dbline 186
0126 ; RX_Mode();
0126 B6D0 rcall _RX_Mode
0128 .dbline 187
0128 ; if((Buffer[0]==80)&&(Buffer[1]==02))//data accept
0128 80910000 lds R24,_Buffer
012C 8035 cpi R24,80
012E 89F4 brne L29
0130 X11:
0130 80910100 lds R24,_Buffer+1
0134 8230 cpi R24,2
0136 69F4 brne L29
0138 X12:
0138 .dbline 188
0138 ; {
0138 .dbline 189
0138 ; accept_flag=1;
0138 81E0 ldi R24,1
013A 80934500 sts _accept_flag,R24
013E .dbline 190
013E ; PORTC = 0x02;
013E 82E0 ldi R24,2
0140 88B9 out 0x8,R24
0142 .dbline 191
0142 ; delayms(5000); //延时10ms*10=100ms
0142 08E8 ldi R16,5000
0144 13E1 ldi R17,19
0146 30D0 rcall _delayms
0148 .dbline 192
0148 ; delayms(5000); //延时10ms*10=100ms
0148 08E8 ldi R16,5000
014A 13E1 ldi R17,19
014C 2DD0 rcall _delayms
014E .dbline 193
014E ; PORTC = 0x00;
014E 2224 clr R2
0150 28B8 out 0x8,R2
0152 .dbline 194
0152 ; }
0152 L29:
0152 .dbline 195
0152 ; }
0152 L23:
0152 .dbline 197
0152 ; //-------------------------------------------
0152 ; }
0152 L19:
0152 .dbline 198
0152 ; }
0152 L3:
0152 .dbline 134
0152 62CF rjmp L2
0154 X13:
0154 .dbline -2
0154 L1:
0154 .dbline 0 ; func end
0154 2196 adiw R28,1
0156 0895 ret
0158 .dbsym r Get_SO 10 c
0158 .dbend
0158 .dbfunc e init_CPU _init_CPU fV
.even
0158 _init_CPU::
0158 .dbline -1
0158 .dbline 207
0158 ;
0158 ;
0158 ; }
0158 ; /*-----------------------------------------------------------------------------
0158 ; Module: init_CPU
0158 ; Function: Initialization of CPU
0158 ; ------------------------------------------------------------------------------*/
0158 ; void init_CPU (void)
0158 ; {
0158 .dbline 208
0158 ; MCUCR = 0x00; //
0158 2224 clr R2
015A 25BE out 0x35,R2
015C .dbline 209
015C ; EICRA = 0x00; //extended ext ints
015C 20926900 sts 105,R2
0160 .dbline 210
0160 ; EIMSK = 0x00;
0160 2DBA out 0x1d,R2
0162 .dbline 212
0162 ;
0162 ; TIMSK0 = 0x01; //timer 0 interrupt sources
0162 81E0 ldi R24,1
0164 80936E00 sts 110,R24
0168 .dbline 213
0168 ; TIMSK1 = 0x00; //timer 1 interrupt sources
0168 20926F00 sts 111,R2
016C .dbline 214
016C ; TIMSK2 = 0x00; //timer 2 interrupt sources
016C 20927000 sts 112,R2
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