dct_kc.uc

H.264完整的C语言代码和DCT的代码

    B:16 = RF:5:OUT:0:REG:3 VAR: tmp#43 DATATYPE: HALF2,
    U2:IN:0 = B:16 VAR: tmp#43 DATATYPE: HALF2,
    B:17 = RF:9:OUT:0:REG:1 VAR: const#2 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#2 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|tmp#44#||0 VAR: tmp#44 DATATYPE: HALF2,
    RF:10:IN:0:REG:4 = B:31 STAGE:3 VAR: tmp#44 DATATYPE: HALF2,
    B:21 = RF:13:OUT:0:REG:7 VAR: COS_1_plus_COS_3 DATATYPE: HALF2,
    U4:IN:1 = B:21 VAR: COS_1_plus_COS_3 DATATYPE: HALF2,
    B:20 = RF:11:OUT:0:REG:6 VAR: tmp#51 DATATYPE: HALF2,
    U4:IN:0 = B:20 VAR: tmp#51 DATATYPE: HALF2,
    B:19 = RF:12:OUT:0:REG:10 VAR: COS_2 DATATYPE: HALF2,
    U3:IN:1 = B:19 VAR: COS_2 DATATYPE: HALF2,
    B:18 = RF:10:OUT:0:REG:4 VAR: tmp#40 DATATYPE: HALF2,
    U3:IN:0 = B:18 VAR: tmp#40 DATATYPE: HALF2,
    B:38 = RF:18:OUT:1:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:2 = B:38 VAR: hw_const#0 DATATYPE: ANYINT,
    B:8 = RF:2:OUT:0:REG:2 VAR: d0734 DATATYPE: HALF2,
    U7:IN:0 = B:8 VAR: d0734 DATATYPE: HALF2,
    B:27 = U7:OUT:0 INSTR_LOG:1|d0734#||0 VAR: d0734 DATATYPE: HALF2,
    RF:4:IN:0:REG:5 = B:27 STAGE:3 VAR: d0734 DATATYPE: HALF2,
    RF:5:IN:0:REG:3 = B:27 STAGE:3 VAR: d0734 DATATYPE: HALF2,
    B:30 = U1:OUT:0 INSTR_LOG:2|s0734#||0 VAR: s0734 DATATYPE: HALF2,
    RF:8:IN:0:REG:5 = B:30 STAGE:3 VAR: s0734 DATATYPE: HALF2,
    RF:6:IN:0:REG:6 = B:30 STAGE:3 VAR: s0734 DATATYPE: HALF2,
    B:14 = RF:4:OUT:0:REG:3 VAR: s16 DATATYPE: HALF2,
    U1:IN:0 = B:14 VAR: s16 DATATYPE: HALF2,
    B:15 = RF:8:OUT:0:REG:6 VAR: s25 DATATYPE: HALF2,
    U1:IN:1 = B:15 VAR: s25 DATATYPE: HALF2,
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:10 = RF:6:OUT:0:REG:10 VAR: a2 DATATYPE: HALF2,
    U5:IN:0 = B:10 VAR: a2 DATATYPE: HALF2,
    B:28 = U5:OUT:0 INSTR_LOG:1|a2#||0 VAR: a2 DATATYPE: HALF2,
    RF:13:IN:0:REG:11 = B:28 STAGE:1 VAR: a2 DATATYPE: HALF2,
    RF:9:IN:0:REG:6 = B:28 STAGE:1 VAR: a2 DATATYPE: HALF2,
    //  IN:SP_SCHED_READ_0: ( a2 ) = SPREAD_WT( hw_const#0 == SPIDXRF_0[0], buf2 == SP_SCHED_RF_0[0] )
    //  IN:SP_SCHED_WRITE_0: ( buf2 ) = SPWRITE( idx1 == SPIDXRF_1[1], tmp#101 == UNITRF_0_0[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf2 == SP_SCHED_RF_0[0] )
    //  IN:ADDER_0: ( tmp#48 ) = SHIFT16( tmp#47 == UNITRF_0_2[4], const#2 == UNITRF_1_1[1] )
    // OUT:ADDER_0: SHIFT16 => ( tmp#48 == MULRF_0_1[6] )
    //  IN:ADDER_2: ( tmp#44 ) = SHIFT16( tmp#43 == UNITRF_0_4[3], const#2 == UNITRF_1_3[1] )
    // OUT:ADDER_2: SHIFT16 => ( tmp#44 == MULRF_0_0[4] )
    //  IN:MULTIPLIER_1: ( m8, tmp#53 ) = IMULRND16( COS_1_plus_COS_3 == MULRF_1_1[7], tmp#51 == MULRF_0_1[6] )
    //  IN:MULTIPLIER_0: ( m5, tmp#42 ) = IMULRND16( COS_2 == MULRF_1_0[10], tmp#40 == MULRF_0_0[4] )
    //  IN:COMM_SCHED_0: ( d0734 ) = NSELECT( hw_const#0 == CCRF_0[0], d0734 == UNITRF_0_1[2] )
    // OUT:COMM_SCHED_0: NSELECT => ( d0734 == UNITRF_0_3[5], d0734 == UNITRF_0_4[3] )
    // OUT:ADDER_1: IADD16 => ( s0734 == UNITRF_1_2[5], s0734 == UNITRF_1_0[6] )
    //  IN:ADDER_1: ( d1625 ) = ISUB16( s16 == UNITRF_0_3[3], s25 == UNITRF_1_2[6] )
    //  IN:DIVIDER_0: ( a2 ) = NSELECT( hw_const#0 == CCRF_0[0], a2 == UNITRF_1_0[10] )
    // OUT:DIVIDER_0: NSELECT => ( a2 == MULRF_1_1[11], a2 == UNITRF_1_3[6] )
    DEAD_REGS: {  };
instr: 27
    MC: OP: NONE LINE:-1,
    U6: OP: SPREAD LINE:191 SP_BASE:3 STAGE:4, // D:\working\im_apps\h264\dct_kc.i:191
    U4: OP: IMULRND16 LINE:152 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:152
    U3: OP: IMULRND16 LINE:151 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:151
    U5: OP: NSELECT LINE:-1 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:-1
    U0: OP: ISUB16 LINE:138 STAGE:2, // D:\working\im_apps\h264\dct_kc.i:138
    U2: OP: IADD16 LINE:126 STAGE:1, // D:\working\im_apps\h264\dct_kc.i:126
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:26 = U6:OUT:0 INSTR_LOG:2|a2#||0 VAR: a2 DATATYPE: HALF2,
    RF:7:IN:0:REG:4 = B:26 STAGE:4 VAR: a2 DATATYPE: HALF2,
    RF:5:IN:0:REG:2 = B:26 STAGE:4 VAR: a2 DATATYPE: HALF2,
    B:21 = RF:13:OUT:0:REG:8 VAR: COS_3 DATATYPE: HALF2,
    U4:IN:1 = B:21 VAR: COS_3 DATATYPE: HALF2,
    B:20 = RF:11:OUT:0:REG:6 VAR: tmp#48 DATATYPE: HALF2,
    U4:IN:0 = B:20 VAR: tmp#48 DATATYPE: HALF2,
    B:19 = RF:12:OUT:0:REG:10 VAR: COS_2 DATATYPE: HALF2,
    U3:IN:1 = B:19 VAR: COS_2 DATATYPE: HALF2,
    B:18 = RF:10:OUT:0:REG:4 VAR: tmp#44 DATATYPE: HALF2,
    U3:IN:0 = B:18 VAR: tmp#44 DATATYPE: HALF2,
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:10 = RF:6:OUT:0:REG:6 VAR: s0734 DATATYPE: HALF2,
    U5:IN:0 = B:10 VAR: s0734 DATATYPE: HALF2,
    B:28 = U5:OUT:0 INSTR_LOG:1|s0734#||0 VAR: s0734 DATATYPE: HALF2,
    RF:4:IN:0:REG:4 = B:28 STAGE:3 VAR: s0734 DATATYPE: HALF2,
    B:12 = RF:3:OUT:0:REG:2 VAR: s07 DATATYPE: HALF2,
    U0:IN:0 = B:12 VAR: s07 DATATYPE: HALF2,
    B:13 = RF:7:OUT:0:REG:4 VAR: s34 DATATYPE: HALF2,
    U0:IN:1 = B:13 VAR: s34 DATATYPE: HALF2,
    B:30 = U1:OUT:0 INSTR_LOG:2|d1625#||0 VAR: d1625 DATATYPE: HALF2,
    RF:8:IN:0:REG:7 = B:30 STAGE:2 VAR: d1625 DATATYPE: HALF2,
    B:17 = RF:9:OUT:0:REG:6 VAR: a2 DATATYPE: HALF2,
    U2:IN:1 = B:17 VAR: a2 DATATYPE: HALF2,
    B:16 = RF:5:OUT:0:REG:2 VAR: a5 DATATYPE: HALF2,
    U2:IN:0 = B:16 VAR: a5 DATATYPE: HALF2,
    //  IN:SP_SCHED_READ_0: ( a3 ) = SPREAD( hw_const#0 == SPIDXRF_0[0], buf2 == SP_SCHED_RF_0[0] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( a2 == UNITRF_1_1[4], a2 == UNITRF_0_4[2] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf2 == SP_SCHED_RF_0[0] )
    //  IN:MULTIPLIER_1: ( m7, tmp#50 ) = IMULRND16( COS_3 == MULRF_1_1[8], tmp#48 == MULRF_0_1[6] )
    //  IN:MULTIPLIER_0: ( m6, tmp#46 ) = IMULRND16( COS_2 == MULRF_1_0[10], tmp#44 == MULRF_0_0[4] )
    //  IN:DIVIDER_0: ( s0734 ) = NSELECT( hw_const#0 == CCRF_0[0], s0734 == UNITRF_1_0[6] )
    // OUT:DIVIDER_0: NSELECT => ( s0734 == UNITRF_0_3[4] )
    //  IN:ADDER_0: ( d0734 ) = ISUB16( s07 == UNITRF_0_2[2], s34 == UNITRF_1_1[4] )
    // OUT:ADDER_1: ISUB16 => ( d1625 == UNITRF_1_2[7] )
    //  IN:ADDER_2: ( s25 ) = IADD16( a2 == UNITRF_1_3[6], a5 == UNITRF_0_4[2] )
    DEAD_REGS: {  };
instr: 28
    MC: OP: NONE LINE:-1,
    U6: OP: SPREAD LINE:192 SP_BASE:4 STAGE:4, // D:\working\im_apps\h264\dct_kc.i:192
    U1: OP: IADD16 LINE:148 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:148
    U3: OP: SELECT LINE:-1 STAGE:2, // D:\working\im_apps\h264\dct_kc.i:-1
    U0: OP: IADD16 LINE:125 STAGE:1, // D:\working\im_apps\h264\dct_kc.i:125
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:26 = U6:OUT:0 INSTR_LOG:2|a3#||0 VAR: a3 DATATYPE: HALF2,
    RF:8:IN:0:REG:5 = B:26 STAGE:4 VAR: a3 DATATYPE: HALF2,
    RF:3:IN:0:REG:2 = B:26 STAGE:4 VAR: a3 DATATYPE: HALF2,
    B:15 = RF:8:OUT:0:REG:5 VAR: s0734 DATATYPE: HALF2,
    U1:IN:1 = B:15 VAR: s0734 DATATYPE: HALF2,
    B:14 = RF:4:OUT:0:REG:1 VAR: s1625 DATATYPE: HALF2,
    U1:IN:0 = B:14 VAR: s1625 DATATYPE: HALF2,
    B:29 = U0:OUT:0 INSTR_LOG:2|d0734#||0 VAR: d0734 DATATYPE: HALF2,
    RF:4:IN:0:REG:1 = B:29 STAGE:2 VAR: d0734 DATATYPE: HALF2,
    RF:2:IN:0:REG:2 = B:29 STAGE:2 VAR: d0734 DATATYPE: HALF2,
    B:43 = RF:18:OUT:6:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U3:IN:2 = B:43 VAR: hw_const#0 DATATYPE: ANYINT,
    B:19 = RF:12:OUT:0:REG:12 VAR: a1 DATATYPE: HALF2,
    U3:IN:1 = B:19 VAR: a1 DATATYPE: HALF2,
    B:33 = U3:OUT:1 INSTR_LOG:1|a1#||1 VAR: a1 DATATYPE: HALF2,
    RF:5:IN:0:REG:4 = B:33 STAGE:2 VAR: a1 DATATYPE: HALF2,
    B:13 = RF:7:OUT:0:REG:5 VAR: a1 DATATYPE: HALF2,
    U0:IN:1 = B:13 VAR: a1 DATATYPE: HALF2,
    B:12 = RF:3:OUT:0:REG:1 VAR: a6 DATATYPE: HALF2,
    U0:IN:0 = B:12 VAR: a6 DATATYPE: HALF2,
    B:31 = U2:OUT:0 INSTR_LOG:2|s25#||0 VAR: s25 DATATYPE: HALF2,
    RF:6:IN:0:REG:6 = B:31 STAGE:1 VAR: s25 DATATYPE: HALF2,
    //  IN:SP_SCHED_READ_0: ( a4 ) = SPREAD( hw_const#0 == SPIDXRF_0[0], buf2 == SP_SCHED_RF_0[0] )
    // OUT:SP_SCHED_READ_0: SPREAD => ( a3 == UNITRF_1_2[5], a3 == UNITRF_0_2[2] )
    //  IN:ADDER_1: ( m1_over_2 ) = IADD16( s0734 == UNITRF_1_2[5], s1625 == UNITRF_0_3[1] )
    // OUT:ADDER_0: ISUB16 => ( d0734 == UNITRF_0_3[1], d0734 == UNITRF_0_1[2] )
    //  IN:MULTIPLIER_0: ( a1 ) = SELECT( hw_const#0 == CCRF_0[0], a1 == MULRF_1_0[12] )
    // OUT:MULTIPLIER_0: SELECT => ( a1 == UNITRF_0_4[4] )
    //  IN:ADDER_0: ( s16 ) = IADD16( a1 == UNITRF_1_1[5], a6 == UNITRF_0_2[1] )
    // OUT:ADDER_2: IADD16 => ( s25 == UNITRF_1_0[6] )
    DEAD_REGS: {  };
instr: 29
    MC: OP: NONE LINE:-1,
    U6: OP: SPREAD LINE:188 SP_BASE:0 STAGE:4, // D:\working\im_apps\h264\dct_kc.i:188
    U2: OP: SHIFT16 LINE:154 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:154
    U1: OP: ISUB16 LINE:149 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:149
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:26 = U6:OUT:0 INSTR_LOG:2|a4#||0 VAR: a4 DATATYPE: HALF2,
    RF:4:IN:0:REG:4 = B:26 STAGE:4 VAR: a4 DATATYPE: HALF2,
    RF:7:IN:0:REG:5 = B:26 STAGE:4 VAR: a4 DATATYPE: HALF2,
    B:16 = RF:5:OUT:0:REG:1 VAR: sd25d34 DATATYPE: HALF2,
    U2:IN:0 = B:16 VAR: sd25d34 DATATYPE: HALF2,
    B:17 = RF:9:OUT:0:REG:1 VAR: const#2 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#2 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|tmp#54#||0 VAR: tmp#54 DATATYPE: HALF2,
    RF:10:IN:0:REG:4 = B:31 STAGE:3 VAR: tmp#54 DATATYPE: HALF2,
    B:35 = U4:OUT:1 INSTR_LOG:4|m8#||1 VAR: m8 DATATYPE: HALF2,
    RF:5:IN:0:REG:1 = B:35 STAGE:3 VAR: m8 DATATYPE: HALF2,
    B:33 = U3:OUT:1 INSTR_LOG:4|m5#||1 VAR: m5 DATATYPE: HALF2,
    RF:9:IN:0:REG:6 = B:33 STAGE:3 VAR: m5 DATATYPE: HALF2,
    RF:8:IN:0:REG:8 = B:33 STAGE:3 VAR: m5 DATATYPE: HALF2,
    B:14 = RF:4:OUT:0:REG:4 VAR: s0734 DATATYPE: HALF2,
    U1:IN:0 = B:14 VAR: s0734 DATATYPE: HALF2,
    B:15 = RF:8:OUT:0:REG:4 VAR: s1625 DATATYPE: HALF2,
    U1:IN:1 = B:15 VAR: s1625 DATATYPE: HALF2,
    B:30 = U1:OUT:0 INSTR_LOG:2|m1_over_2#||0 VAR: m1_over_2 DATATYPE: HALF2,
    RF:3:IN:0:REG:1 = B:30 STAGE:3 VAR: m1_over_2 DATATYPE: HALF2,
    B:29 = U0:OUT:0 INSTR_LOG:2|s16#||0 VAR: s16 DATATYPE: HALF2,
    RF:12:IN:0:REG:11 = B:29 STAGE:1 VAR: s16 DATATYPE: HALF2,
    //  IN:SP_SCHED_READ_0: ( a0 ) = SPREAD( hw_const#0 == SPIDXRF_0[0], buf2 == SP_SCHED_RF_0[0] )
    // OUT:SP_SCHED_READ_0: SPREAD => ( a4 == UNITRF_0_3[4], a4 == UNITRF_1_1[5] )
    //  IN:ADDER_2: ( tmp#54 ) = SHIFT16( sd25d34 == UNITRF_0_4[1], const#2 == UNITRF_1_3[1] )
    // OUT:ADDER_2: SHIFT16 => ( tmp#54 == MULRF_0_0[4] )
    // OUT:MULTIPLIER_1: IMULRND16 => ( m8 == UNITRF_0_4[1] )
    // OUT:MULTIPLIER_0: IMULRND16 => ( m5 == UNITRF_1_3[6], m5 == UNITRF_1_2[8] )
    //  IN:ADDER_1: ( m2 ) = ISUB16( s0734 == UNITRF_0_3[4], s1625 == UNITRF_1_2[4] )
    // OUT:ADDER_1: IADD16 => ( m1_over_2 == UNITRF_0_2[1] )
    // OUT:ADDER_0: IADD16 => ( s16 == MULRF_1_0[11] )
    DEAD_REGS: {  };
instr: 30
    MC: OP: NONE LINE:-1,
    U6: OP: SPREAD LINE:189 SP_BASE:1 STAGE:4, // D:\working\im_apps\h264\dct_kc.i:189
    U3: OP: IMULRND16 LINE:154 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:154
    U2: OP: IADD16 LINE:169 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:169
    U0: OP: SHIFT16 LINE:167 STAGE:3, // D:\working\im_apps\h264\dct_kc.i:167
    U1: OP: IADD16 LINE:128 STAGE:2, // D:\working\im_apps\h264\dct_kc.i:128
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:26 = U6:OUT:0 INSTR_LOG:2|a0#||0 VAR: a0 DATATYPE: HALF2,
    RF:8:IN:0:REG:6 = B:26 STAGE:4 VAR: a0 DATATYPE: HALF2,
    RF:4:IN:0:REG:3 = B:26 STAGE:4 VAR: a0 DATATYPE: HALF2,
    B:19 = RF:12:OUT:0:REG:6 VAR: COS_1_minus_COS_3 DATATYPE: HALF2,
    U3:IN:1 = B:19 VAR: COS_1_minus_COS_3 DATATYPE: HALF2,
    B:18 = RF:10:OUT:0:REG:4 VAR: tmp#54 DATATYPE: HALF2,
    U3:IN:0 = B:18 VAR: tmp#54 DATATYPE: HALF2,
    B:35 = U4:OUT:1 INSTR_LOG:4|m7#||1 VAR: m7 DATATYPE: HALF2,
    RF:9:IN:0:REG:6 = B:35 STAGE:3 VAR: m7 DATATYPE: HALF2,
    RF:7:IN:0:REG:6 = B:35 STAGE:3 VAR: m7 DATATYPE: HALF2,
    B:33 = U3:OUT:1 INSTR_LOG:4|m6#||1 VAR: m6 DATATYPE: HALF2,
    RF:5:IN:0:REG:3 = B:33 STAGE:3 VAR: m6 DATATYPE: HALF2,
    RF:6:IN:0:REG:9 = B:33 STAGE:3 VAR: m6 DATATYPE: HALF2,
    B:16 = RF:5:OUT:0:REG:3 VAR: d0734 DATATYPE: HALF2,
    U2:IN:0 = B:16 VAR: d0734 DATATYPE: HALF2,
    B:17 = RF:9:OUT:0:REG:6 VA