📄 mv2idx_kc.uc
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RF:4:IN:0:REG:5 = B:31 STAGE:1 VAR: fetchx DATATYPE: UINT,
RF:5:IN:0:REG:3 = B:31 STAGE:1 VAR: fetchx DATATYPE: UINT,
B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
B:6 = RF:1:OUT:0:REG:1 VAR: tmp#12 DATATYPE: UNDEFINED,
U6:IN:1 = B:6 VAR: tmp#12 DATATYPE: UNDEFINED,
B:3 = RF:19:OUT:3:REG:1 VAR: jb_motion#0 DATATYPE: UNDEFINED,
U6:IN:4 = B:3 VAR: jb_motion#0 DATATYPE: UNDEFINED,
// IN:ADDER_2: ( fetchy ) = IADD32( yrefy == UNITRF_1_3[10], dy == UNITRF_0_4[3] )
// OUT:ADDER_2: IADD32 => ( fetchx == UNITRF_0_2[5], fetchx == UNITRF_0_3[5], fetchx == UNITRF_0_4[3] )
// IN:SP_SCHED_WRITE_0: ( sp_motion#0 ) = SPCWRITE( hw_const#0 == SPIDXRF_1[0], tmp#12 == UNITRF_0_0[1], jb_motion#0 == JBRF_0[1] )
DEAD_REGS: { };
instr: 22
MC: OP: NONE LINE:-1,
B:31 = U2:OUT:0 INSTR_LOG:2|fetchy#||0 VAR: fetchy DATATYPE: UINT,
RF:3:IN:0:REG:4 = B:31 STAGE:1 VAR: fetchy DATATYPE: UINT,
RF:5:IN:0:REG:4 = B:31 STAGE:1 VAR: fetchy DATATYPE: UINT,
RF:9:IN:0:REG:13 = B:31 STAGE:1 VAR: fetchy DATATYPE: UINT,
// OUT:ADDER_2: IADD32 => ( fetchy == UNITRF_0_2[4], fetchy == UNITRF_0_4[4], fetchy == UNITRF_1_3[13] )
// OUT:SP_SCHED_WRITE_0: SPCWRITE => ( sp_motion#0 == SP_SCHED_RF_0[0] )
DEAD_REGS: { };
instr: 23
MC: OP: NONE LINE:-1,
U2: OP: IADD32 LINE:72 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:72
U0: OP: SHIFT32 LINE:82 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:82
B:17 = RF:9:OUT:0:REG:13 VAR: fetchy DATATYPE: UINT,
U2:IN:1 = B:17 VAR: fetchy DATATYPE: UINT,
B:16 = RF:5:OUT:0:REG:2 VAR: const#8 DATATYPE: ANYINT,
U2:IN:0 = B:16 VAR: const#8 DATATYPE: ANYINT,
B:12 = RF:3:OUT:0:REG:5 VAR: fetchx DATATYPE: UINT,
U0:IN:0 = B:12 VAR: fetchx DATATYPE: UINT,
B:13 = RF:7:OUT:0:REG:8 VAR: const#-4 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#-4 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|tmp#38#||0 VAR: tmp#38 DATATYPE: UINT,
RF:4:IN:0:REG:4 = B:29 STAGE:1 VAR: tmp#38 DATATYPE: UINT,
// IN:ADDER_2: ( fetchy ) = IADD32( fetchy == UNITRF_1_3[13], const#8 == UNITRF_0_4[2] )
// IN:ADDER_0: ( tmp#38 ) = SHIFT32( fetchx == UNITRF_0_2[5], const#-4 == UNITRF_1_1[8] )
// OUT:ADDER_0: SHIFT32 => ( tmp#38 == UNITRF_0_3[4] )
DEAD_REGS: { };
instr: 24
MC: OP: NONE LINE:-1,
U0: OP: SHIFT32 LINE:70 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:70
U1: OP: SHIFT32 LINE:82 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:82
B:31 = U2:OUT:0 INSTR_LOG:2|fetchy#||0 VAR: fetchy DATATYPE: UINT,
RF:3:IN:0:REG:4 = B:31 STAGE:1 VAR: fetchy DATATYPE: UINT,
RF:4:IN:0:REG:4 = B:31 STAGE:1 VAR: fetchy DATATYPE: UINT,
B:12 = RF:3:OUT:0:REG:4 VAR: fetchy DATATYPE: UINT,
U0:IN:0 = B:12 VAR: fetchy DATATYPE: UINT,
B:13 = RF:7:OUT:0:REG:8 VAR: const#-4 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#-4 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|tmp#18#||0 VAR: tmp#18 DATATYPE: UINT,
RF:11:IN:0:REG:2 = B:29 STAGE:1 VAR: tmp#18 DATATYPE: UINT,
B:14 = RF:4:OUT:0:REG:4 VAR: tmp#38 DATATYPE: UINT,
U1:IN:0 = B:14 VAR: tmp#38 DATATYPE: UINT,
B:15 = RF:8:OUT:0:REG:5 VAR: const#6 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: const#6 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|tmp#41#||0 VAR: tmp#41 DATATYPE: UINT,
RF:10:IN:0:REG:1 = B:30 STAGE:1 VAR: tmp#41 DATATYPE: UINT,
// OUT:ADDER_2: IADD32 => ( fetchy == UNITRF_0_2[4], fetchy == UNITRF_0_3[4] )
// IN:ADDER_0: ( tmp#18 ) = SHIFT32( fetchy == UNITRF_0_2[4], const#-4 == UNITRF_1_1[8] )
// OUT:ADDER_0: SHIFT32 => ( tmp#18 == MULRF_0_1[2] )
// IN:ADDER_1: ( tmp#41 ) = SHIFT32( tmp#38 == UNITRF_0_3[4], const#6 == UNITRF_1_2[5] )
// OUT:ADDER_1: SHIFT32 => ( tmp#41 == MULRF_0_0[1] )
DEAD_REGS: { };
instr: 25
MC: OP: NONE LINE:-1,
U0: OP: SHIFT32 LINE:73 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:73
U4: OP: UMUL32 LINE:70 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:70
U2: OP: SHIFT32 LINE:79 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:79
U1: OP: AND LINE:83 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:83
B:12 = RF:3:OUT:0:REG:4 VAR: fetchy DATATYPE: UINT,
U0:IN:0 = B:12 VAR: fetchy DATATYPE: UINT,
B:13 = RF:7:OUT:0:REG:8 VAR: const#-4 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#-4 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|tmp#23#||0 VAR: tmp#23 DATATYPE: UINT,
RF:10:IN:0:REG:2 = B:29 STAGE:1 VAR: tmp#23 DATATYPE: UINT,
B:20 = RF:11:OUT:0:REG:2 VAR: tmp#18 DATATYPE: UINT,
U4:IN:0 = B:20 VAR: tmp#18 DATATYPE: UINT,
B:21 = RF:13:OUT:0:REG:3 VAR: rowlen DATATYPE: UINT,
U4:IN:1 = B:21 VAR: rowlen DATATYPE: UINT,
B:16 = RF:5:OUT:0:REG:5 VAR: fetchx DATATYPE: UINT,
U2:IN:0 = B:16 VAR: fetchx DATATYPE: UINT,
B:17 = RF:9:OUT:0:REG:9 VAR: const#-4 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#-4 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|tmp#33#||0 VAR: tmp#33 DATATYPE: UINT,
RF:4:IN:0:REG:5 = B:31 STAGE:1 VAR: tmp#33 DATATYPE: UINT,
B:14 = RF:4:OUT:0:REG:5 VAR: fetchx DATATYPE: UINT,
U1:IN:0 = B:14 VAR: fetchx DATATYPE: UINT,
B:15 = RF:8:OUT:0:REG:4 VAR: const#15 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: const#15 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|tmp#39#||0 VAR: tmp#39 DATATYPE: UINT,
RF:5:IN:0:REG:5 = B:30 STAGE:1 VAR: tmp#39 DATATYPE: UINT,
// IN:ADDER_0: ( tmp#23 ) = SHIFT32( fetchy == UNITRF_0_2[4], const#-4 == UNITRF_1_1[8] )
// OUT:ADDER_0: SHIFT32 => ( tmp#23 == MULRF_0_0[2] )
// IN:MULTIPLIER_1: ( tmp#19, tmp#20 ) = UMUL32( tmp#18 == MULRF_0_1[2], rowlen == MULRF_1_1[3] )
// IN:ADDER_2: ( tmp#33 ) = SHIFT32( fetchx == UNITRF_0_4[5], const#-4 == UNITRF_1_3[9] )
// OUT:ADDER_2: SHIFT32 => ( tmp#33 == UNITRF_0_3[5] )
// IN:ADDER_1: ( tmp#39 ) = AND( fetchx == UNITRF_0_3[5], const#15 == UNITRF_1_2[4] )
// OUT:ADDER_1: AND => ( tmp#39 == UNITRF_0_4[5] )
DEAD_REGS: { };
instr: 26
MC: OP: NONE LINE:-1,
U3: OP: UMUL32 LINE:73 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:73
U0: OP: AND LINE:77 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:77
U1: OP: SHIFT32 LINE:79 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:79
U2: OP: SHIFT32 LINE:83 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:83
B:18 = RF:10:OUT:0:REG:2 VAR: tmp#23 DATATYPE: UINT,
U3:IN:0 = B:18 VAR: tmp#23 DATATYPE: UINT,
B:19 = RF:12:OUT:0:REG:2 VAR: rowlen DATATYPE: UINT,
U3:IN:1 = B:19 VAR: rowlen DATATYPE: UINT,
B:12 = RF:3:OUT:0:REG:3 VAR: fetchx DATATYPE: UINT,
U0:IN:0 = B:12 VAR: fetchx DATATYPE: UINT,
B:13 = RF:7:OUT:0:REG:6 VAR: const#15 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#15 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|tmp#29#||0 VAR: tmp#29 DATATYPE: UINT,
RF:5:IN:0:REG:5 = B:29 STAGE:1 VAR: tmp#29 DATATYPE: UINT,
B:14 = RF:4:OUT:0:REG:5 VAR: tmp#33 DATATYPE: UINT,
U1:IN:0 = B:14 VAR: tmp#33 DATATYPE: UINT,
B:15 = RF:8:OUT:0:REG:5 VAR: const#6 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: const#6 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|tmp#36#||0 VAR: tmp#36 DATATYPE: UINT,
RF:8:IN:0:REG:10 = B:30 STAGE:1 VAR: tmp#36 DATATYPE: UINT,
B:16 = RF:5:OUT:0:REG:5 VAR: tmp#39 DATATYPE: UINT,
U2:IN:0 = B:16 VAR: tmp#39 DATATYPE: UINT,
B:17 = RF:9:OUT:0:REG:7 VAR: const#-2 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#-2 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|tmp#40#||0 VAR: tmp#40 DATATYPE: UINT,
RF:6:IN:0:REG:2 = B:31 STAGE:1 VAR: tmp#40 DATATYPE: UINT,
// IN:MULTIPLIER_0: ( tmp#24, tmp#25 ) = UMUL32( tmp#23 == MULRF_0_0[2], rowlen == MULRF_1_0[2] )
// IN:ADDER_0: ( tmp#29 ) = AND( fetchx == UNITRF_0_2[3], const#15 == UNITRF_1_1[6] )
// OUT:ADDER_0: AND => ( tmp#29 == UNITRF_0_4[5] )
// IN:ADDER_1: ( tmp#36 ) = SHIFT32( tmp#33 == UNITRF_0_3[5], const#6 == UNITRF_1_2[5] )
// OUT:ADDER_1: SHIFT32 => ( tmp#36 == UNITRF_1_2[10] )
// IN:ADDER_2: ( tmp#40 ) = SHIFT32( tmp#39 == UNITRF_0_4[5], const#-2 == UNITRF_1_3[7] )
// OUT:ADDER_2: SHIFT32 => ( tmp#40 == UNITRF_1_0[2] )
DEAD_REGS: { };
instr: 27
MC: OP: NONE LINE:-1,
U2: OP: SHIFT32 LINE:77 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:77
U1: OP: AND LINE:80 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:80
U0: OP: SHIFT32 LINE:76 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:76
B:16 = RF:5:OUT:0:REG:5 VAR: tmp#29 DATATYPE: UINT,
U2:IN:0 = B:16 VAR: tmp#29 DATATYPE: UINT,
B:17 = RF:9:OUT:0:REG:7 VAR: const#-2 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#-2 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|tmp#30#||0 VAR: tmp#30 DATATYPE: UINT,
RF:4:IN:0:REG:3 = B:31 STAGE:1 VAR: tmp#30 DATATYPE: UINT,
B:14 = RF:4:OUT:0:REG:3 VAR: fetchx DATATYPE: UINT,
U1:IN:0 = B:14 VAR: fetchx DATATYPE: UINT,
B:15 = RF:8:OUT:0:REG:4 VAR: const#15 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: const#15 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|tmp#34#||0 VAR: tmp#34 DATATYPE: UINT,
RF:5:IN:0:REG:5 = B:30 STAGE:1 VAR: tmp#34 DATATYPE: UINT,
B:12 = RF:3:OUT:0:REG:3 VAR: fetchx DATATYPE: UINT,
U0:IN:0 = B:12 VAR: fetchx DATATYPE: UINT,
B:13 = RF:7:OUT:0:REG:8 VAR: const#-4 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#-4 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|tmp#28#||0 VAR: tmp#28 DATATYPE: UINT,
RF:3:IN:0:REG:3 = B:29 STAGE:1 VAR: tmp#28 DATATYPE: UINT,
// IN:ADDER_2: ( tmp#30 ) = SHIFT32( tmp#29 == UNITRF_0_4[5], const#-2 == UNITRF_1_3[7] )
// OUT:ADDER_2: SHIFT32 => ( tmp#30 == UNITRF_0_3[3] )
// IN:ADDER_1: ( tmp#34 ) = AND( fetchx == UNITRF_0_3[3], const#15 == UNITRF_1_2[4] )
// OUT:ADDER_1: AND => ( tmp#34 == UNITRF_0_4[5] )
// IN:ADDER_0: ( tmp#28 ) = SHIFT32( fetchx == UNITRF_0_2[3], const#-4 == UNITRF_1_1[8] )
// OUT:ADDER_0: SHIFT32 => ( tmp#28 == UNITRF_0_2[3] )
DEAD_REGS: { };
instr: 28
MC: OP: NONE LINE:-1,
U1: OP: SHIFT32 LINE:77 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:77
U2: OP: SHIFT32 LINE:80 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:80
U0: OP: SHIFT32 LINE:76 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:76
B:14 = RF:4:OUT:0:REG:3 VAR: tmp#30 DATATYPE: UINT,
U1:IN:0 = B:14 VAR: tmp#30 DATATYPE: UINT,
B:15 = RF:8:OUT:0:REG:3 VAR: const#4 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: const#4 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|tmp#32#||0 VAR: tmp#32 DATATYPE: UINT,
RF:3:IN:0:REG:3 = B:30 STAGE:1 VAR: tmp#32 DATATYPE: UINT,
B:16 = RF:5:OUT:0:REG:5 VAR: tmp#34 DATATYPE: UINT,
U2:IN:0 = B:16 VAR: tmp#34 DATATYPE: UINT,
B:17 = RF:9:OUT:0:REG:7 VAR: const#-2 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#-2 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|tmp#35#||0 VAR: tmp#35 DATATYPE: UINT,
RF:5:IN:0:REG:5 = B:31 STAGE:1 VAR: tmp#35 DATATYPE: UINT,
B:34 = U4:OUT:0 INSTR_LOG:4|tmp#20#||0 VAR: tmp#20 DATATYPE: UINT,
RF:4:IN:0:REG:3 = B:34 STAGE:1 VAR: tmp#20 DATATYPE: UINT,
B:12 = RF:3:OUT:0:REG:3 VAR: tmp#28 DATATYPE: UINT,
U0:IN:0 = B:12 VAR: tmp#28 DATATYPE: UINT,
B:13 = RF:7:OUT:0:REG:7 VAR: const#6 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#6 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|tmp#31#||0 VAR: tmp#31 DATATYPE: UINT,
RF:7:IN:0:REG:9 = B:29 STAGE:1 VAR: tmp#31 DATATYPE: UINT,
// IN:ADDER_1: ( tmp#32 ) = SHIFT32( tmp#30 == UNITRF_0_3[3], const#4 == UNITRF_1_2[3] )
// OUT:ADDER_1: SHIFT32 => ( tmp#32 == UNITRF_0_2[3] )
// IN:ADDER_2: ( tmp#35 ) = SHIFT32( tmp#34 == UNITRF_0_4[5], const#-2 == UNITRF_1_3[7] )
// OUT:ADDER_2: SHIFT32 => ( tmp#35 == UNITRF_0_4[5] )
// OUT:MULTIPLIER_1: UMUL32 => ( tmp#20 == UNITRF_0_3[3] )
// IN:ADDER_0: ( tmp#31 ) = SHIFT32( tmp#28 == UNITRF_0_2[3], const#6 == UNITRF_1_1[7] )
// OUT:ADDER_0: SHIFT32 => ( tmp#31 == UNITRF_1_1[9] )
DEAD_REGS: { };
instr: 29
MC: OP: NONE LINE:-1,
U1: OP: SHIFT32 LINE:70 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:70
U2: OP: AND LINE:71 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:71
U0: OP: IADD32 LINE:77 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:77
U5: OP: NSELECT LINE:-1 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
B:32 = U3:OUT:0 INSTR_LOG:4|tmp#25#||0 VAR: tmp#25 DATATYPE: UINT,
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