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📄 mv2idx_kc.uc

📁 H.264完整的C语言代码和DCT的代码
💻 UC
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    B:15 = RF:8:OUT:0:REG:8 VAR: ccend DATATYPE: CC,
    U1:IN:1 = B:15 VAR: ccend DATATYPE: CC,
    B:46 = U1:OUT:0 INSTR_LOG:1|ccend#||0 VAR: ccend DATATYPE: CC,
    RF:18:IN:0:REG:2 = B:46 STAGE:-1 VAR: ccend DATATYPE: CC,
    //  IN:MC_0: ( ) = NLOOP( tmp#7 == UCONDRF_0[1] )
    //  IN:ADDER_2: ( crefx ) = IADD32( tmp#5 == UNITRF_1_3[10], cluster#id == UNITRF_0_4[1] )
    // OUT:ADDER_0: IADD32 => ( yrefy == UNITRF_1_3[10] )
    //  IN:MULTIPLIER_1: ( const#0 ) = NSELECT( hw_const#0 == CCRF_0[0], hw_const#0 == MULRF_0_1[0] )
    // OUT:MULTIPLIER_1: NSELECT => ( const#0 == UNITRF_1_2[9] )
    //  IN:COMM_SCHED_0: ( unpackmv ) = COMMUCDATA( hw_const#8 == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_const#0x57571302 == UCRF_0[4] )
    // OUT:COMM_SCHED_0: COMMUCDATA => ( unpackmv == MULRF_1_1[1] )
    //  IN:MULTIPLIER_0: ( mb_width ) = NSELECT( hw_const#0 == CCRF_0[0], mb_width == MULRF_0_0[2] )
    // OUT:MULTIPLIER_0: NSELECT => ( mb_width == UNITRF_0_4[2] )
    //  IN:SP_SCHED_WRITE_0: ( sp_motion#0 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#1 == UNITRF_0_0[1] )
    //  IN:ADDER_1: ( ccend ) = SELECT( hw_const#0 == CCRF_0[0], ccend == UNITRF_1_2[8] )
    // OUT:ADDER_1: SELECT => ( ccend == CCRF_0[2] )
    DEAD_REGS: {  };
instr: 15
    MC: OP: NONE LINE:-1,
    U4: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
    U1: OP: SHIFT32 LINE:35 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:35
    U0: OP: SHIFT32 LINE:29 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:29
    U3: OP: NSELECT LINE:31 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:31
    U8: OP: INIT_CISTATE LINE:9 STR_ID:0 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:9
    B:44 = RF:18:OUT:7:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U4:IN:2 = B:44 VAR: hw_const#0 DATATYPE: ANYINT,
    B:20 = RF:11:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U4:IN:0 = B:20 VAR: hw_const#0 DATATYPE: ANYINT,
    B:35 = U4:OUT:1 INSTR_LOG:1|const#0#||1 VAR: const#0 DATATYPE: ANYINT,
    RF:9:IN:0:REG:11 = B:35 STAGE:-1 VAR: const#0 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:2|crefx#||0 VAR: crefx DATATYPE: INT,
    RF:3:IN:0:REG:1 = B:31 STAGE:-1 VAR: crefx DATATYPE: INT,
    RF:5:IN:0:REG:1 = B:31 STAGE:-1 VAR: crefx DATATYPE: INT,
    B:14 = RF:4:OUT:0:REG:1 VAR: yoffset DATATYPE: INT,
    U1:IN:0 = B:14 VAR: yoffset DATATYPE: INT,
    B:15 = RF:8:OUT:0:REG:1 VAR: const#-1 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: const#-1 DATATYPE: ANYINT,
    B:30 = U1:OUT:0 INSTR_LOG:1|crefy#||0 VAR: crefy DATATYPE: INT,
    RF:8:IN:0:REG:8 = B:30 STAGE:-1 VAR: crefy DATATYPE: INT,
    B:12 = RF:3:OUT:0:REG:1 VAR: mb_width DATATYPE: UINT,
    U0:IN:0 = B:12 VAR: mb_width DATATYPE: UINT,
    B:13 = RF:7:OUT:0:REG:7 VAR: const#6 DATATYPE: ANYINT,
    U0:IN:1 = B:13 VAR: const#6 DATATYPE: ANYINT,
    B:29 = U0:OUT:0 INSTR_LOG:1|crowlen#||0 VAR: crowlen DATATYPE: UINT,
    RF:13:IN:0:REG:2 = B:29 STAGE:-1 VAR: crowlen DATATYPE: UINT,
    RF:12:IN:0:REG:1 = B:29 STAGE:-1 VAR: crowlen DATATYPE: UINT,
    B:43 = RF:18:OUT:6:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U3:IN:2 = B:43 VAR: hw_const#0 DATATYPE: ANYINT,
    B:18 = RF:10:OUT:0:REG:1 VAR: xoffset DATATYPE: INT,
    U3:IN:0 = B:18 VAR: xoffset DATATYPE: INT,
    B:33 = U3:OUT:1 INSTR_LOG:1|yrefx#||1 VAR: yrefx DATATYPE: INT,
    RF:7:IN:0:REG:8 = B:33 STAGE:-1 VAR: yrefx DATATYPE: INT,
    RF:4:IN:0:REG:1 = B:33 STAGE:-1 VAR: yrefx DATATYPE: INT,
    B:49 = U8:OUT:0 INSTR_LOG:1|jb_motion#0#||0 VAR: jb_motion#0 DATATYPE: UNDEFINED,
    RF:19:IN:0:REG:2 = B:49 STAGE:-1 VAR: jb_motion#0 DATATYPE: UNDEFINED,
    //  IN:MULTIPLIER_1: ( const#0 ) = NSELECT( hw_const#0 == CCRF_0[0], hw_const#0 == MULRF_0_1[0] )
    // OUT:MULTIPLIER_1: NSELECT => ( const#0 == UNITRF_1_3[11] )
    // OUT:ADDER_2: IADD32 => ( crefx == UNITRF_0_2[1], crefx == UNITRF_0_4[1] )
    //  IN:ADDER_1: ( crefy ) = SHIFT32( yoffset == UNITRF_0_3[1], const#-1 == UNITRF_1_2[1] )
    // OUT:ADDER_1: SHIFT32 => ( crefy == UNITRF_1_2[8] )
    //  IN:ADDER_0: ( crowlen ) = SHIFT32( mb_width == UNITRF_0_2[1], const#6 == UNITRF_1_1[7] )
    // OUT:ADDER_0: SHIFT32 => ( crowlen == MULRF_1_1[2], crowlen == MULRF_1_0[1] )
    //  IN:MULTIPLIER_0: ( yrefx ) = NSELECT( hw_const#0 == CCRF_0[0], xoffset == MULRF_0_0[1] )
    // OUT:MULTIPLIER_0: NSELECT => ( yrefx == UNITRF_1_1[8], yrefx == UNITRF_0_3[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( sp_motion#0 == SP_SCHED_RF_0[0] )
    // OUT:JUKEBOX_SCHED_0: INIT_CISTATE => ( jb_motion#0 == JBRF_0[2] )
    DEAD_REGS: {  };
instr: 16
    MC: OP: NONE LINE:-1,
    U3: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
    U7: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
    U2: OP: SHIFT32 LINE:28 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:28
    U4: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
    U5: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
    U1: OP: IEQ32 LINE:42 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:42
    U0: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
    U9: OP: PASS LINE:-1 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
    U8: OP: PASS LINE:-1 STAGE:-1, // D:\working\im_apps\h264\mv2idx_kc.i:-1
    B:43 = RF:18:OUT:6:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U3:IN:2 = B:43 VAR: hw_const#0 DATATYPE: ANYINT,
    B:18 = RF:10:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U3:IN:0 = B:18 VAR: hw_const#0 DATATYPE: ANYINT,
    B:33 = U3:OUT:1 INSTR_LOG:1|const#0#||1 VAR: const#0 DATATYPE: ANYINT,
    RF:8:IN:0:REG:9 = B:33 STAGE:-1 VAR: const#0 DATATYPE: ANYINT,
    RF:14:IN:0:REG:1 = B:33 STAGE:-1 VAR: const#0 DATATYPE: ANYINT,
    B:38 = RF:18:OUT:1:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:2 = B:38 VAR: hw_const#0 DATATYPE: ANYINT,
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|const#8#||0 VAR: const#8 DATATYPE: ANYINT,
    RF:5:IN:0:REG:2 = B:27 STAGE:-1 VAR: const#8 DATATYPE: ANYINT,
    RF:9:IN:0:REG:12 = B:27 STAGE:-1 VAR: const#8 DATATYPE: ANYINT,
    B:16 = RF:5:OUT:0:REG:2 VAR: mb_width DATATYPE: UINT,
    U2:IN:0 = B:16 VAR: mb_width DATATYPE: UINT,
    B:17 = RF:9:OUT:0:REG:12 VAR: const#2 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#2 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|rowlen#||0 VAR: rowlen DATATYPE: UINT,
    RF:13:IN:0:REG:3 = B:31 STAGE:-1 VAR: rowlen DATATYPE: UINT,
    RF:12:IN:0:REG:2 = B:31 STAGE:-1 VAR: rowlen DATATYPE: UINT,
    B:44 = RF:18:OUT:7:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U4:IN:2 = B:44 VAR: hw_const#0 DATATYPE: ANYINT,
    B:20 = RF:11:OUT:0:REG:1 VAR: const#-4 DATATYPE: ANYINT,
    U4:IN:0 = B:20 VAR: const#-4 DATATYPE: ANYINT,
    B:35 = U4:OUT:1 INSTR_LOG:1|const#-4#||1 VAR: const#-4 DATATYPE: ANYINT,
    RF:7:IN:0:REG:8 = B:35 STAGE:-1 VAR: const#-4 DATATYPE: ANYINT,
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:10 = RF:6:OUT:0:REG:1 VAR: const#7 DATATYPE: ANYINT,
    U5:IN:0 = B:10 VAR: const#7 DATATYPE: ANYINT,
    B:28 = U5:OUT:0 INSTR_LOG:1|const#7#||0 VAR: const#7 DATATYPE: ANYINT,
    RF:4:IN:0:REG:2 = B:28 STAGE:-1 VAR: const#7 DATATYPE: ANYINT,
    B:14 = RF:4:OUT:0:REG:2 VAR: cluster#id DATATYPE: ANYINT,
    U1:IN:0 = B:14 VAR: cluster#id DATATYPE: ANYINT,
    B:15 = RF:8:OUT:0:REG:9 VAR: const#0 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: const#0 DATATYPE: ANYINT,
    B:46 = U1:OUT:0 INSTR_LOG:1|ccin#||0 VAR: ccin DATATYPE: CC,
    RF:18:IN:0:REG:3 = B:46 STAGE:-1 VAR: ccin DATATYPE: CC,
    B:40 = RF:18:OUT:3:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U0:IN:2 = B:40 VAR: hw_const#0 DATATYPE: ANYINT,
    B:13 = RF:7:OUT:0:REG:8 VAR: yrefx DATATYPE: INT,
    U0:IN:1 = B:13 VAR: yrefx DATATYPE: INT,
    B:29 = U0:OUT:0 INSTR_LOG:1|yrefx#||0 VAR: yrefx DATATYPE: INT,
    RF:3:IN:0:REG:2 = B:29 STAGE:-1 VAR: yrefx DATATYPE: INT,
    B:4 = RF:20:OUT:0:REG:1 VAR: vld_motion#0 DATATYPE: UNDEFINED,
    U9:IN:1 = B:4 VAR: vld_motion#0 DATATYPE: UNDEFINED,
    B:51 = U9:OUT:0 INSTR_LOG:1|vld_motion#0#||0 VAR: vld_motion#0 DATATYPE: UNDEFINED,
    RF:20:IN:0:REG:1 = B:51 STAGE:-1 VAR: vld_motion#0 DATATYPE: UNDEFINED,
    B:0 = RF:19:OUT:0:REG:2 VAR: jb_motion#0 DATATYPE: UNDEFINED,
    U8:IN:0 = B:0 VAR: jb_motion#0 DATATYPE: UNDEFINED,
    B:49 = U8:OUT:0 INSTR_LOG:1|jb_motion#0#||0 VAR: jb_motion#0 DATATYPE: UNDEFINED,
    RF:19:IN:0:REG:1 = B:49 STAGE:-1 VAR: jb_motion#0 DATATYPE: UNDEFINED,
    //  IN:MULTIPLIER_0: ( const#0 ) = NSELECT( hw_const#0 == CCRF_0[0], hw_const#0 == MULRF_0_0[0] )
    // OUT:MULTIPLIER_0: NSELECT => ( const#0 == UNITRF_1_2[9], const#0 == UNITRF_CID_0[1] )
    //  IN:COMM_SCHED_0: ( const#8 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#8 == PERMRF_0[0] )
    // OUT:COMM_SCHED_0: SELECT => ( const#8 == UNITRF_0_4[2], const#8 == UNITRF_1_3[12] )
    //  IN:ADDER_2: ( rowlen ) = SHIFT32( mb_width == UNITRF_0_4[2], const#2 == UNITRF_1_3[12] )
    // OUT:ADDER_2: SHIFT32 => ( rowlen == MULRF_1_1[3], rowlen == MULRF_1_0[2] )
    //  IN:MULTIPLIER_1: ( const#-4 ) = NSELECT( hw_const#0 == CCRF_0[0], const#-4 == MULRF_0_1[1] )
    // OUT:MULTIPLIER_1: NSELECT => ( const#-4 == UNITRF_1_1[8] )
    //  IN:DIVIDER_0: ( const#7 ) = NSELECT( hw_const#0 == CCRF_0[0], const#7 == UNITRF_1_0[1] )
    // OUT:DIVIDER_0: NSELECT => ( const#7 == UNITRF_0_3[2] )
    //  IN:ADDER_1: ( ccin ) = IEQ32( cluster#id == UNITRF_0_3[2], const#0 == UNITRF_1_2[9] )
    // OUT:ADDER_1: IEQ32 => ( ccin == CCRF_0[3] )
    //  IN:ADDER_0: ( yrefx ) = SELECT( hw_const#0 == CCRF_0[0], yrefx == UNITRF_1_1[8] )
    // OUT:ADDER_0: SELECT => ( yrefx == UNITRF_0_2[2] )
    //  IN:VALID_SCHED_0: ( vld_motion#0 ) = PASS( vld_motion#0 == VALIDRF_0[1] )
    // OUT:VALID_SCHED_0: PASS => ( vld_motion#0 == VALIDRF_0[1] )
    //  IN:JUKEBOX_SCHED_0: ( jb_motion#0 ) = PASS( jb_motion#0 == JBRF_0[2] )
    // OUT:JUKEBOX_SCHED_0: PASS => ( jb_motion#0 == JBRF_0[1] )
    DEAD_REGS: {  };
instr: 17
    MC: OP: NONE LINE:-1,
    B:29 = U0:OUT:0 INSTR_LOG:2|fetchx#||0 VAR: fetchx DATATYPE: UINT,
    RF:3:IN:0:REG:3 = B:29 STAGE:1 VAR: fetchx DATATYPE: UINT,
    RF:4:IN:0:REG:3 = B:29 STAGE:1 VAR: fetchx DATATYPE: UINT,
    // OUT:ADDER_0: IADD32 => ( fetchx == UNITRF_0_2[3], fetchx == UNITRF_0_3[3] )
    DEAD_REGS: {  };
instr: 18
    MC: OP: NONE LINE:-1,
    U1: OP: IADD32 LINE:78 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:78
    U9: OP: GEN_CCEND LINE:53 STR_ID:0 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:53
    B:14 = RF:4:OUT:0:REG:3 VAR: fetchx DATATYPE: UINT,
    U1:IN:0 = B:14 VAR: fetchx DATATYPE: UINT,
    B:15 = RF:8:OUT:0:REG:3 VAR: const#4 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: const#4 DATATYPE: ANYINT,
    B:22 = COND_IN_D:0 STAGE:1 LINE:53 VAR: tmp#12 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:1 = B:22 STAGE:1 VAR: tmp#12 DATATYPE: UNDEFINED,
    B:1 = RF:19:OUT:1:REG:1 VAR: jb_motion#0 DATATYPE: UNDEFINED,
    U9:IN:0 = B:1 VAR: jb_motion#0 DATATYPE: UNDEFINED,
    B:4 = RF:20:OUT:0:REG:2 VAR: vld_motion#0 DATATYPE: UNDEFINED,
    U9:IN:1 = B:4 VAR: vld_motion#0 DATATYPE: UNDEFINED,
    B:51 = U9:OUT:0 INSTR_LOG:1|vld_motion#0#|ccend#||0|1 VAR: vld_motion#0 DATATYPE: UNDEFINED,
    RF:20:IN:0:REG:1 = B:51 STAGE:1 VAR: vld_motion#0 DATATYPE: UNDEFINED,
    B:48 = U9:OUT:1 INSTR_LOG:1|vld_motion#0#|ccend#||0|1 VAR: ccend DATATYPE: CC,
    RF:18:IN:1:REG:2 = B:48 STAGE:1 VAR: ccend DATATYPE: CC,
    //  IN:ADDER_1: ( fetchx ) = IADD32( fetchx == UNITRF_0_3[3], const#4 == UNITRF_1_2[3] )
    // OUT:INOUT_0: COND_IN_D => ( tmp#12 == UNITRF_0_0[1] )
    //  IN:VALID_SCHED_0: ( vld_motion#0, ccend ) = GEN_CCEND( jb_motion#0 == JBRF_0[1], vld_motion#0 == VALIDRF_0[2] )
    // OUT:VALID_SCHED_0: GEN_CCEND => ( vld_motion#0 == VALIDRF_0[1], ccend == CCRF_0[2] )
    DEAD_REGS: {  };
instr: 19
    MC: OP: NONE LINE:-1,
    B:30 = U1:OUT:0 INSTR_LOG:2|fetchx#||0 VAR: fetchx DATATYPE: UINT,
    RF:5:IN:0:REG:5 = B:30 STAGE:1 VAR: fetchx DATATYPE: UINT,
    RF:4:IN:0:REG:3 = B:30 STAGE:1 VAR: fetchx DATATYPE: UINT,
    // OUT:ADDER_1: IADD32 => ( fetchx == UNITRF_0_4[5], fetchx == UNITRF_0_3[3] )
    DEAD_REGS: {  };
instr: 20
    MC: OP: NONE LINE:-1,
    U2: OP: IADD32 LINE:81 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:81
    B:16 = RF:5:OUT:0:REG:5 VAR: fetchx DATATYPE: UINT,
    U2:IN:0 = B:16 VAR: fetchx DATATYPE: UINT,
    B:17 = RF:9:OUT:0:REG:4 VAR: const#4 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#4 DATATYPE: ANYINT,
    //  IN:ADDER_2: ( fetchx ) = IADD32( fetchx == UNITRF_0_4[5], const#4 == UNITRF_1_3[4] )
    DEAD_REGS: {  };
instr: 21
    MC: OP: NONE LINE:-1,
    U2: OP: IADD32 LINE:66 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:66
    U6: OP: SPCWRITE LINE:53 SP_BASE:0 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\mv2idx_kc.i:53
    B:17 = RF:9:OUT:0:REG:10 VAR: yrefy DATATYPE: INT,
    U2:IN:1 = B:17 VAR: yrefy DATATYPE: INT,
    B:16 = RF:5:OUT:0:REG:3 VAR: dy DATATYPE: INT,
    U2:IN:0 = B:16 VAR: dy DATATYPE: INT,
    B:31 = U2:OUT:0 INSTR_LOG:2|fetchx#||0 VAR: fetchx DATATYPE: UINT,
    RF:3:IN:0:REG:5 = B:31 STAGE:1 VAR: fetchx DATATYPE: UINT,

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