diff_kc.uc

H.264完整的C语言代码和DCT的代码

    //  IN:ADDER_1: ( tmp#48 ) = OR( d1_second == UNITRF_1_2[1], d3_second == UNITRF_0_3[2] )
    // OUT:ADDER_1: OR => ( tmp#48 == UNITRF_0_0[1] )
    //  IN:SP_SCHED_WRITE_0: ( buf1 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#47 == UNITRF_0_0[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf1 == SP_SCHED_RF_0[0] )
    // OUT:ADDER_0: ISUB16 => ( diffy#12 == MULRF_0_1[1] )
    //  IN:SP_SCHED_READ_0: ( tmp#92 ) = SPREAD_WT( idx4 == SPIDXRF_0[4], buf3 == SP_SCHED_RF_0[8] )
    //  IN:ADDER_2: ( diffy#5 ) = ISUB16( currhi#2 == UNITRF_0_4[2], refhi#2 == UNITRF_1_3[1] )
    DEAD_REGS: {  };
instr: 27
    MC: OP: NONE LINE:-1,
    U6: OP: SPWRITE LINE:212 SP_BASE:2 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:212
    U4: OP: SHUFFLED LINE:225 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:225
    U1: OP: OR LINE:213 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:213
    U6: OP: SPREAD_WT LINE:301 SP_BASE:8 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:301
    U2: OP: ISUB16 LINE:198 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:198
    U3: OP: SHUFFLED LINE:221 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:221
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:1 VAR: tmp#48 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#48 DATATYPE: UNDEFINED,
    B:20 = RF:11:OUT:0:REG:1 VAR: diffy#12 DATATYPE: HALF2,
    U4:IN:0 = B:20 VAR: diffy#12 DATATYPE: HALF2,
    B:21 = RF:13:OUT:0:REG:1 VAR: h2_to_2hi DATATYPE: BYTE4,
    U4:IN:1 = B:21 VAR: h2_to_2hi DATATYPE: BYTE4,
    B:35 = U4:OUT:1 INSTR_LOG:1|d2_first#|d2_second#||1|0 VAR: d2_first DATATYPE: HALF2,
    RF:5:IN:0:REG:1 = B:35 STAGE:1 VAR: d2_first DATATYPE: HALF2,
    B:34 = U4:OUT:0 INSTR_LOG:1|d2_first#|d2_second#||1|0 VAR: d2_second DATATYPE: HALF2,
    RF:3:IN:0:REG:1 = B:34 STAGE:1 VAR: d2_second DATATYPE: HALF2,
    B:14 = RF:4:OUT:0:REG:1 VAR: d1_first DATATYPE: HALF2,
    U1:IN:0 = B:14 VAR: d1_first DATATYPE: HALF2,
    B:15 = RF:8:OUT:0:REG:2 VAR: d3_first DATATYPE: HALF2,
    U1:IN:1 = B:15 VAR: d3_first DATATYPE: HALF2,
    B:30 = U1:OUT:0 INSTR_LOG:1|tmp#49#||0 VAR: tmp#49 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:1 = B:30 STAGE:1 VAR: tmp#49 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:5 VAR: idx5 DATATYPE: INT,
    U6:IN:0 = B:5 VAR: idx5 DATATYPE: INT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#92#||0 VAR: tmp#92 DATATYPE: HALF2,
    RF:2:IN:0:REG:2 = B:26 STAGE:1 VAR: tmp#92 DATATYPE: HALF2,
    B:16 = RF:5:OUT:0:REG:1 VAR: currhi#6 DATATYPE: HALF2,
    U2:IN:0 = B:16 VAR: currhi#6 DATATYPE: HALF2,
    B:17 = RF:9:OUT:0:REG:2 VAR: refhi#6 DATATYPE: HALF2,
    U2:IN:1 = B:17 VAR: refhi#6 DATATYPE: HALF2,
    B:18 = RF:10:OUT:0:REG:1 VAR: diffy#4 DATATYPE: HALF2,
    U3:IN:0 = B:18 VAR: diffy#4 DATATYPE: HALF2,
    B:19 = RF:12:OUT:0:REG:2 VAR: h2_to_2lo DATATYPE: BYTE4,
    U3:IN:1 = B:19 VAR: h2_to_2lo DATATYPE: BYTE4,
    B:33 = U3:OUT:1 INSTR_LOG:1|d0_first#|d0_second#||1|0 VAR: d0_first DATATYPE: HALF2,
    RF:9:IN:0:REG:1 = B:33 STAGE:1 VAR: d0_first DATATYPE: HALF2,
    B:32 = U3:OUT:0 INSTR_LOG:1|d0_first#|d0_second#||1|0 VAR: d0_second DATATYPE: HALF2,
    RF:7:IN:0:REG:1 = B:32 STAGE:1 VAR: d0_second DATATYPE: HALF2,
    B:31 = U2:OUT:0 INSTR_LOG:2|diffy#5#||0 VAR: diffy#5 DATATYPE: HALF2,
    RF:11:IN:0:REG:1 = B:31 STAGE:1 VAR: diffy#5 DATATYPE: HALF2,
    //  IN:SP_SCHED_WRITE_0: ( buf1 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#48 == UNITRF_0_0[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf1 == SP_SCHED_RF_0[0] )
    //  IN:MULTIPLIER_1: ( d2_first, d2_second ) = SHUFFLED( diffy#12 == MULRF_0_1[1], h2_to_2hi == MULRF_1_1[1] )
    // OUT:MULTIPLIER_1: SHUFFLED => ( d2_first == UNITRF_0_4[1], d2_second == UNITRF_0_2[1] )
    //  IN:ADDER_1: ( tmp#49 ) = OR( d1_first == UNITRF_0_3[1], d3_first == UNITRF_1_2[2] )
    // OUT:ADDER_1: OR => ( tmp#49 == UNITRF_0_0[1] )
    //  IN:SP_SCHED_READ_0: ( tmp#94 ) = SPREAD_WT( idx5 == SPIDXRF_0[5], buf3 == SP_SCHED_RF_0[8] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#92 == UNITRF_0_1[2] )
    //  IN:ADDER_2: ( diffy#13 ) = ISUB16( currhi#6 == UNITRF_0_4[1], refhi#6 == UNITRF_1_3[2] )
    //  IN:MULTIPLIER_0: ( d0_first, d0_second ) = SHUFFLED( diffy#4 == MULRF_0_0[1], h2_to_2lo == MULRF_1_0[2] )
    // OUT:MULTIPLIER_0: SHUFFLED => ( d0_first == UNITRF_1_3[1], d0_second == UNITRF_1_1[1] )
    // OUT:ADDER_2: ISUB16 => ( diffy#5 == MULRF_0_1[1] )
    DEAD_REGS: {  };
instr: 28
    MC: OP: NONE LINE:-1,
    U0: OP: OR LINE:228 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:228
    U6: OP: SPWRITE LINE:213 SP_BASE:3 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:213
    U6: OP: SPREAD_WT LINE:299 SP_BASE:8 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:299
    B:13 = RF:7:OUT:0:REG:1 VAR: d0_second DATATYPE: HALF2,
    U0:IN:1 = B:13 VAR: d0_second DATATYPE: HALF2,
    B:12 = RF:3:OUT:0:REG:1 VAR: d2_second DATATYPE: HALF2,
    U0:IN:0 = B:12 VAR: d2_second DATATYPE: HALF2,
    B:29 = U0:OUT:0 INSTR_LOG:1|tmp#50#||0 VAR: tmp#50 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:1 = B:29 STAGE:1 VAR: tmp#50 DATATYPE: UNDEFINED,
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:1 VAR: tmp#49 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#49 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:3 VAR: idx3 DATATYPE: INT,
    U6:IN:0 = B:5 VAR: idx3 DATATYPE: INT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#94#||0 VAR: tmp#94 DATATYPE: HALF2,
    RF:2:IN:0:REG:1 = B:26 STAGE:1 VAR: tmp#94 DATATYPE: HALF2,
    B:31 = U2:OUT:0 INSTR_LOG:2|diffy#13#||0 VAR: diffy#13 DATATYPE: HALF2,
    RF:10:IN:0:REG:1 = B:31 STAGE:1 VAR: diffy#13 DATATYPE: HALF2,
    //  IN:ADDER_0: ( tmp#50 ) = OR( d0_second == UNITRF_1_1[1], d2_second == UNITRF_0_2[1] )
    // OUT:ADDER_0: OR => ( tmp#50 == UNITRF_0_0[1] )
    //  IN:SP_SCHED_WRITE_0: ( buf1 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#49 == UNITRF_0_0[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf1 == SP_SCHED_RF_0[0] )
    //  IN:SP_SCHED_READ_0: ( tmp#90 ) = SPREAD_WT( idx3 == SPIDXRF_0[3], buf3 == SP_SCHED_RF_0[8] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#94 == UNITRF_0_1[1] )
    // OUT:ADDER_2: ISUB16 => ( diffy#13 == MULRF_0_0[1] )
    DEAD_REGS: {  };
instr: 29
    MC: OP: NONE LINE:-1,
    U6: OP: SPWRITE LINE:228 SP_BASE:4 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:228
    U2: OP: OR LINE:229 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:229
    U6: OP: SPREAD_WT LINE:302 SP_BASE:8 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:302
    U3: OP: SHUFFLED LINE:226 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:226
    U4: OP: SHUFFLED LINE:222 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:222
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:1 VAR: tmp#50 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#50 DATATYPE: UNDEFINED,
    B:17 = RF:9:OUT:0:REG:1 VAR: d0_first DATATYPE: HALF2,
    U2:IN:1 = B:17 VAR: d0_first DATATYPE: HALF2,
    B:16 = RF:5:OUT:0:REG:1 VAR: d2_first DATATYPE: HALF2,
    U2:IN:0 = B:16 VAR: d2_first DATATYPE: HALF2,
    B:31 = U2:OUT:0 INSTR_LOG:1|tmp#51#||0 VAR: tmp#51 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:1 = B:31 STAGE:1 VAR: tmp#51 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:6 VAR: idx6 DATATYPE: INT,
    U6:IN:0 = B:5 VAR: idx6 DATATYPE: INT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#90#||0 VAR: tmp#90 DATATYPE: HALF2,
    RF:2:IN:0:REG:5 = B:26 STAGE:1 VAR: tmp#90 DATATYPE: HALF2,
    B:18 = RF:10:OUT:0:REG:1 VAR: diffy#13 DATATYPE: HALF2,
    U3:IN:0 = B:18 VAR: diffy#13 DATATYPE: HALF2,
    B:19 = RF:12:OUT:0:REG:1 VAR: h2_to_2hi DATATYPE: BYTE4,
    U3:IN:1 = B:19 VAR: h2_to_2hi DATATYPE: BYTE4,
    B:33 = U3:OUT:1 INSTR_LOG:1|d3_first#|d3_second#||1|0 VAR: d3_first DATATYPE: HALF2,
    RF:4:IN:0:REG:1 = B:33 STAGE:1 VAR: d3_first DATATYPE: HALF2,
    B:32 = U3:OUT:0 INSTR_LOG:1|d3_first#|d3_second#||1|0 VAR: d3_second DATATYPE: HALF2,
    RF:3:IN:0:REG:1 = B:32 STAGE:1 VAR: d3_second DATATYPE: HALF2,
    B:20 = RF:11:OUT:0:REG:1 VAR: diffy#5 DATATYPE: HALF2,
    U4:IN:0 = B:20 VAR: diffy#5 DATATYPE: HALF2,
    B:21 = RF:13:OUT:0:REG:2 VAR: h2_to_2lo DATATYPE: BYTE4,
    U4:IN:1 = B:21 VAR: h2_to_2lo DATATYPE: BYTE4,
    B:35 = U4:OUT:1 INSTR_LOG:1|d1_first#|d1_second#||1|0 VAR: d1_first DATATYPE: HALF2,
    RF:8:IN:0:REG:1 = B:35 STAGE:1 VAR: d1_first DATATYPE: HALF2,
    B:34 = U4:OUT:0 INSTR_LOG:1|d1_first#|d1_second#||1|0 VAR: d1_second DATATYPE: HALF2,
    RF:7:IN:0:REG:1 = B:34 STAGE:1 VAR: d1_second DATATYPE: HALF2,
    //  IN:SP_SCHED_WRITE_0: ( buf1 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#50 == UNITRF_0_0[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf1 == SP_SCHED_RF_0[0] )
    //  IN:ADDER_2: ( tmp#51 ) = OR( d0_first == UNITRF_1_3[1], d2_first == UNITRF_0_4[1] )
    // OUT:ADDER_2: OR => ( tmp#51 == UNITRF_0_0[1] )
    //  IN:SP_SCHED_READ_0: ( tmp#96 ) = SPREAD_WT( idx6 == SPIDXRF_0[6], buf3 == SP_SCHED_RF_0[8] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#90 == UNITRF_0_1[5] )
    //  IN:MULTIPLIER_0: ( d3_first, d3_second ) = SHUFFLED( diffy#13 == MULRF_0_0[1], h2_to_2hi == MULRF_1_0[1] )
    // OUT:MULTIPLIER_0: SHUFFLED => ( d3_first == UNITRF_0_3[1], d3_second == UNITRF_0_2[1] )
    //  IN:MULTIPLIER_1: ( d1_first, d1_second ) = SHUFFLED( diffy#5 == MULRF_0_1[1], h2_to_2lo == MULRF_1_1[2] )
    // OUT:MULTIPLIER_1: SHUFFLED => ( d1_first == UNITRF_1_2[1], d1_second == UNITRF_1_1[1] )
    DEAD_REGS: {  };
instr: 30
    MC: OP: NONE LINE:-1,
    U6: OP: SPWRITE LINE:229 SP_BASE:5 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:229
    U6: OP: SPREAD_WT LINE:298 SP_BASE:8 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:298
    U0: OP: OR LINE:230 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:230
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:1 VAR: tmp#51 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#51 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:2 VAR: idx2 DATATYPE: INT,
    U6:IN:0 = B:5 VAR: idx2 DATATYPE: INT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#96#||0 VAR: tmp#96 DATATYPE: HALF2,
    RF:2:IN:0:REG:3 = B:26 STAGE:1 VAR: tmp#96 DATATYPE: HALF2,
    B:13 = RF:7:OUT:0:REG:1 VAR: d1_second DATATYPE: HALF2,
    U0:IN:1 = B:13 VAR: d1_second DATATYPE: HALF2,
    B:12 = RF:3:OUT:0:REG:1 VAR: d3_second DATATYPE: HALF2,
    U0:IN:0 = B:12 VAR: d3_second DATATYPE: HALF2,
    B:29 = U0:OUT:0 INSTR_LOG:1|tmp#52#||0 VAR: tmp#52 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:1 = B:29 STAGE:1 VAR: tmp#52 DATATYPE: UNDEFINED,
    //  IN:SP_SCHED_WRITE_0: ( buf1 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#51 == UNITRF_0_0[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf1 == SP_SCHED_RF_0[0] )
    //  IN:SP_SCHED_READ_0: ( tmp#88 ) = SPREAD_WT( idx2 == SPIDXRF_0[2], buf3 == SP_SCHED_RF_0[8] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#96 == UNITRF_0_1[3] )
    //  IN:ADDER_0: ( tmp#52 ) = OR( d1_second == UNITRF_1_1[1], d3_second == UNITRF_0_2[1] )
    // OUT:ADDER_0: OR => ( tmp#52 == UNITRF_0_0[1] )
    DEAD_REGS: {  };
instr: 31
    MC: OP: NONE LINE:-1,
    U6: OP: SPWRITE LINE:230 SP_BASE:6 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:230
    U6: OP: SPREAD_WT LINE:303 SP_BASE:8 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:303
    U1: OP: OR LINE:231 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:231
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:1 VAR: tmp#52 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#52 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:7 VAR: idx7 DATATYPE: INT,
    U6:IN:0 = B:5 VAR: idx7 DATATYPE: INT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#88#||0 VAR: tmp#88 DATATYPE: HALF2,
    RF:2:IN:0:REG:6 = B:26 STAGE:1 VAR: tmp#88 DATATYPE: HALF2,
    B:15 = RF:8:OUT:0:REG:1 VAR: d1_first DATATYPE: HALF2,
    U1:IN:1 = B:15 VAR: d1_first DATATYPE: HALF2,
    B:14 = RF:4:OUT:0:REG:1 VAR: d3_first DATATYPE: HALF2,
    U1:IN:0 = B:14 VAR: d3_first DATATYPE: HALF2,
    B:30 = U1:OUT:0 INSTR_LOG:1|tmp#53#||0 VAR: tmp#53 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:1 = B:30 STAGE:1 VAR: tmp#53 DATATYPE: UNDEFINED,
    //  IN:SP_SCHED_WRITE_0: ( buf1 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#52 == UNITRF_0_0[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf1 == SP_SCHED_RF_0[0] )
    //  IN:SP_SCHED_READ_0: ( tmp#98 ) = SPREAD_WT( idx7 == SPIDXRF_0[7], buf3 == SP_SCHED_RF_0[8] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#88 == UNITRF_0_1[6] )
    //  IN:ADDER_1: ( tmp#53 ) = OR( d1_first == UNITRF_1_2[1], d3_first == UNITRF_0_3[1] )
    // OUT:ADDER_1: OR => ( tmp#53 == UNITRF_0_0[1] )
    DEAD_REGS: {  };
instr: 32
    MC: OP: NONE LINE:-1,
    U6: OP: SPREAD_WT LINE:240 SP_BASE:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:240
    U6: OP: SPWRITE LINE:231 SP_BASE:7 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:231
    B:5 = RF:16:OUT:0:REG:1 VAR: idx1 DATATYPE: INT,
    U6:IN:0 = B:5 VAR: idx1 DATATYPE: INT,
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:1 VAR: tmp#53 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#53 DATATYPE: UNDEFINED,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#98#||0 VAR: tmp#98 DATATYPE: HALF2,
    RF:2:IN:0:REG:4 = B:26 STAGE:1 VAR: tmp#98 DATATYPE: HALF2,
    //  IN:SP_SCHED_READ_0: ( tmp#55 ) = SPREAD_WT( idx1 == SPIDXRF_0[1], buf1 == SP_SCHED_RF_0[0] )
    //  IN:SP_SCHED_WRITE_0: ( buf1 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#53 == UNITRF_0_0[1] )