📄 diff_kc.uc
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U2: OP: ISUB32 LINE:45 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:45
B:16 = RF:5:OUT:0:REG:1 VAR: idx4 DATATYPE: INT,
U2:IN:0 = B:16 VAR: idx4 DATATYPE: INT,
B:17 = RF:9:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: hw_const#1 DATATYPE: ANYINT,
// IN:ADDER_2: ( tmp#10 ) = ISUB32( idx4 == UNITRF_0_4[1], hw_const#1 == UNITRF_1_3[0] )
// OUT:MC_0: CHK_EOS => ( tmp#13 == UCONDRF_0[1] )
DEAD_REGS: { };
instr: 16
MC: OP: UC_DATA_IN LINE:31 IMM:0x7654321 UCRF_WR:1 STAGES:-1,
B:31 = U2:OUT:0 INSTR_LOG:2|tmp#10#||0 VAR: tmp#10 DATATYPE: INT,
RF:4:IN:0:REG:1 = B:31 STAGE:-1 VAR: tmp#10 DATATYPE: INT,
// OUT:ADDER_2: ISUB32 => ( tmp#10 == UNITRF_0_3[1] )
// OUT:MC_0: UC_DATA_IN => ( perm_a == UCRF_0[1] )
DEAD_REGS: { };
instr: 17
MC: OP: UC_DATA_IN LINE:32 IMM:0x10765432 UCRF_WR:2 STAGES:-1,
U1: OP: AND LINE:45 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:45
B:14 = RF:4:OUT:0:REG:1 VAR: tmp#10 DATATYPE: INT,
U1:IN:0 = B:14 VAR: tmp#10 DATATYPE: INT,
B:15 = RF:8:OUT:0:REG:1 VAR: const#7 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: const#7 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|idx5#||0 VAR: idx5 DATATYPE: INT,
RF:3:IN:0:REG:1 = B:30 STAGE:-1 VAR: idx5 DATATYPE: INT,
RF:17:IN:0:REG:5 = B:30 STAGE:-1 VAR: idx5 DATATYPE: INT,
RF:16:IN:0:REG:5 = B:30 STAGE:-1 VAR: idx5 DATATYPE: INT,
// IN:ADDER_1: ( idx5 ) = AND( tmp#10 == UNITRF_0_3[1], const#7 == UNITRF_1_2[1] )
// OUT:ADDER_1: AND => ( idx5 == UNITRF_0_2[1], idx5 == SPIDXRF_1[5], idx5 == SPIDXRF_0[5] )
// OUT:MC_0: UC_DATA_IN => ( perm_b == UCRF_0[2] )
DEAD_REGS: { };
instr: 18
MC: OP: UC_DATA_IN LINE:33 IMM:0x21076543 UCRF_WR:3 STAGES:-1,
U0: OP: ISUB32 LINE:46 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:46
B:12 = RF:3:OUT:0:REG:1 VAR: idx5 DATATYPE: INT,
U0:IN:0 = B:12 VAR: idx5 DATATYPE: INT,
B:13 = RF:7:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: hw_const#1 DATATYPE: ANYINT,
// IN:ADDER_0: ( tmp#11 ) = ISUB32( idx5 == UNITRF_0_2[1], hw_const#1 == UNITRF_1_1[0] )
// OUT:MC_0: UC_DATA_IN => ( perm_c == UCRF_0[3] )
DEAD_REGS: { };
instr: 19
MC: OP: UC_DATA_IN LINE:34 IMM:0x32107654 UCRF_WR:4 STAGES:-1,
B:29 = U0:OUT:0 INSTR_LOG:2|tmp#11#||0 VAR: tmp#11 DATATYPE: INT,
RF:5:IN:0:REG:1 = B:29 STAGE:-1 VAR: tmp#11 DATATYPE: INT,
// OUT:ADDER_0: ISUB32 => ( tmp#11 == UNITRF_0_4[1] )
// OUT:MC_0: UC_DATA_IN => ( perm_d == UCRF_0[4] )
DEAD_REGS: { };
instr: 20
MC: OP: UC_DATA_IN LINE:35 IMM:0x43210765 UCRF_WR:5 STAGES:-1,
U2: OP: AND LINE:46 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:46
B:16 = RF:5:OUT:0:REG:1 VAR: tmp#11 DATATYPE: INT,
U2:IN:0 = B:16 VAR: tmp#11 DATATYPE: INT,
B:17 = RF:9:OUT:0:REG:1 VAR: const#7 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#7 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|idx6#||0 VAR: idx6 DATATYPE: INT,
RF:4:IN:0:REG:1 = B:31 STAGE:-1 VAR: idx6 DATATYPE: INT,
RF:17:IN:0:REG:6 = B:31 STAGE:-1 VAR: idx6 DATATYPE: INT,
RF:16:IN:0:REG:6 = B:31 STAGE:-1 VAR: idx6 DATATYPE: INT,
// IN:ADDER_2: ( idx6 ) = AND( tmp#11 == UNITRF_0_4[1], const#7 == UNITRF_1_3[1] )
// OUT:ADDER_2: AND => ( idx6 == UNITRF_0_3[1], idx6 == SPIDXRF_1[6], idx6 == SPIDXRF_0[6] )
// OUT:MC_0: UC_DATA_IN => ( perm_e == UCRF_0[5] )
DEAD_REGS: { };
instr: 21
MC: OP: UC_DATA_IN LINE:36 IMM:0x54321076 UCRF_WR:6 STAGES:-1,
U1: OP: ISUB32 LINE:47 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:47
B:14 = RF:4:OUT:0:REG:1 VAR: idx6 DATATYPE: INT,
U1:IN:0 = B:14 VAR: idx6 DATATYPE: INT,
B:15 = RF:8:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: hw_const#1 DATATYPE: ANYINT,
// IN:ADDER_1: ( tmp#12 ) = ISUB32( idx6 == UNITRF_0_3[1], hw_const#1 == UNITRF_1_2[0] )
// OUT:MC_0: UC_DATA_IN => ( perm_f == UCRF_0[6] )
DEAD_REGS: { };
instr: 22
MC: OP: NLOOP LINE:59 UCRF_RD:10 UCONDRF_RD:1 BR_OFF:35 LAST_STAGE:1,
U7: OP: COMMUCDATA LINE:-1 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:-1
B:30 = U1:OUT:0 INSTR_LOG:2|tmp#12#||0 VAR: tmp#12 DATATYPE: INT,
RF:3:IN:0:REG:1 = B:30 STAGE:-1 VAR: tmp#12 DATATYPE: INT,
B:9 = RF:15:OUT:0:REG:0 VAR: hw_mctrl#id DATATYPE: ANYINT,
U7:IN:1 = B:9 VAR: hw_mctrl#id DATATYPE: ANYINT,
B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
B:27 = U7:OUT:0 INSTR_LOG:1|h2_to_2hi#||0 VAR: h2_to_2hi DATATYPE: BYTE4,
RF:12:IN:0:REG:1 = B:27 STAGE:-1 VAR: h2_to_2hi DATATYPE: BYTE4,
RF:13:IN:0:REG:1 = B:27 STAGE:-1 VAR: h2_to_2hi DATATYPE: BYTE4,
// IN:MC_0: ( ) = NLOOP( tmp#13 == UCONDRF_0[1] )
// OUT:ADDER_1: ISUB32 => ( tmp#12 == UNITRF_0_2[1] )
// IN:COMM_SCHED_0: ( h2_to_2hi ) = COMMUCDATA( hw_mctrl#id == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_const#0x13028888 == UCRF_0[10] )
// OUT:COMM_SCHED_0: COMMUCDATA => ( h2_to_2hi == MULRF_1_0[1], h2_to_2hi == MULRF_1_1[1] )
DEAD_REGS: { };
instr: 23
MC: OP: UC_DATA_IN LINE:37 IMM:0x65432107 UCRF_RD:9 UCRF_WR:7 STAGES:-1,
U0: OP: AND LINE:47 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:47
U7: OP: COMMUCDATA LINE:-1 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:-1
B:12 = RF:3:OUT:0:REG:1 VAR: tmp#12 DATATYPE: INT,
U0:IN:0 = B:12 VAR: tmp#12 DATATYPE: INT,
B:13 = RF:7:OUT:0:REG:1 VAR: const#7 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#7 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|idx7#||0 VAR: idx7 DATATYPE: INT,
RF:17:IN:0:REG:7 = B:29 STAGE:-1 VAR: idx7 DATATYPE: INT,
RF:16:IN:0:REG:7 = B:29 STAGE:-1 VAR: idx7 DATATYPE: INT,
B:9 = RF:15:OUT:0:REG:0 VAR: hw_mctrl#id DATATYPE: ANYINT,
U7:IN:1 = B:9 VAR: hw_mctrl#id DATATYPE: ANYINT,
B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
B:27 = U7:OUT:0 INSTR_LOG:1|h2_to_2lo#||0 VAR: h2_to_2lo DATATYPE: BYTE4,
RF:13:IN:0:REG:2 = B:27 STAGE:-1 VAR: h2_to_2lo DATATYPE: BYTE4,
RF:12:IN:0:REG:2 = B:27 STAGE:-1 VAR: h2_to_2lo DATATYPE: BYTE4,
// IN:ADDER_0: ( idx7 ) = AND( tmp#12 == UNITRF_0_2[1], const#7 == UNITRF_1_1[1] )
// OUT:ADDER_0: AND => ( idx7 == SPIDXRF_1[7], idx7 == SPIDXRF_0[7] )
// OUT:MC_0: UC_DATA_IN => ( perm_g == UCRF_0[7] )
// IN:COMM_SCHED_0: ( h2_to_2lo ) = COMMUCDATA( hw_mctrl#id == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_const#0x88881302 == UCRF_0[9] )
// OUT:COMM_SCHED_0: COMMUCDATA => ( h2_to_2lo == MULRF_1_1[2], h2_to_2lo == MULRF_1_0[2] )
DEAD_REGS: { };
instr: 24
MC: OP: NONE LINE:-1 UCRF_RD:8 END:,
U5: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:-1
U7: OP: COMMUCDATA LINE:-1 STAGE:-1, // D:\working\im_apps\h264\diff_kc.i:-1
B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
B:11 = RF:14:OUT:0:REG:0 VAR: cluster#id DATATYPE: ANYINT,
U5:IN:1 = B:11 VAR: cluster#id DATATYPE: ANYINT,
B:28 = U5:OUT:0 INSTR_LOG:1|cluster#id#||0 VAR: cluster#id DATATYPE: ANYINT,
RF:16:IN:0:REG:8 = B:28 STAGE:-1 VAR: cluster#id DATATYPE: ANYINT,
RF:17:IN:0:REG:8 = B:28 STAGE:-1 VAR: cluster#id DATATYPE: ANYINT,
B:9 = RF:15:OUT:0:REG:0 VAR: hw_mctrl#id DATATYPE: ANYINT,
U7:IN:1 = B:9 VAR: hw_mctrl#id DATATYPE: ANYINT,
B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
B:27 = U7:OUT:0 INSTR_LOG:1|b4_to_2h2#||0 VAR: b4_to_2h2 DATATYPE: BYTE4,
RF:13:IN:0:REG:3 = B:27 STAGE:-1 VAR: b4_to_2h2 DATATYPE: BYTE4,
RF:12:IN:0:REG:3 = B:27 STAGE:-1 VAR: b4_to_2h2 DATATYPE: BYTE4,
// IN:DIVIDER_0: ( cluster#id ) = SELECT( hw_const#0 == CCRF_0[0], cluster#id == UNITRF_CID_0[0] )
// OUT:DIVIDER_0: SELECT => ( cluster#id == SPIDXRF_0[8], cluster#id == SPIDXRF_1[8] )
// IN:COMM_SCHED_0: ( b4_to_2h2 ) = COMMUCDATA( hw_mctrl#id == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_const#0x88138802 == UCRF_0[8] )
// OUT:COMM_SCHED_0: COMMUCDATA => ( b4_to_2h2 == MULRF_1_1[3], b4_to_2h2 == MULRF_1_0[3] )
DEAD_REGS: { };
instr: 25
MC: OP: NONE LINE:-1,
U2: OP: OR LINE:211 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:211
U6: OP: SPWRITE LINE:210 SP_BASE:0 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:210
U0: OP: ISUB16 LINE:197 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:197
U3: OP: SHUFFLED LINE:208 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:208
U7: OP: NSELECT LINE:-1 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:-1
B:17 = RF:9:OUT:0:REG:3 VAR: d0_first DATATYPE: HALF2,
U2:IN:1 = B:17 VAR: d0_first DATATYPE: HALF2,
B:16 = RF:5:OUT:0:REG:2 VAR: d2_first DATATYPE: HALF2,
U2:IN:0 = B:16 VAR: d2_first DATATYPE: HALF2,
B:31 = U2:OUT:0 INSTR_LOG:1|tmp#47#||0 VAR: tmp#47 DATATYPE: UNDEFINED,
RF:1:IN:0:REG:1 = B:31 STAGE:1 VAR: tmp#47 DATATYPE: UNDEFINED,
B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
B:6 = RF:1:OUT:0:REG:1 VAR: tmp#46 DATATYPE: UNDEFINED,
U6:IN:1 = B:6 VAR: tmp#46 DATATYPE: UNDEFINED,
B:12 = RF:3:OUT:0:REG:1 VAR: currlo#6 DATATYPE: HALF2,
U0:IN:0 = B:12 VAR: currlo#6 DATATYPE: HALF2,
B:13 = RF:7:OUT:0:REG:1 VAR: reflo#6 DATATYPE: HALF2,
U0:IN:1 = B:13 VAR: reflo#6 DATATYPE: HALF2,
B:18 = RF:10:OUT:0:REG:1 VAR: diffy#9 DATATYPE: HALF2,
U3:IN:0 = B:18 VAR: diffy#9 DATATYPE: HALF2,
B:19 = RF:12:OUT:0:REG:1 VAR: h2_to_2hi DATATYPE: BYTE4,
U3:IN:1 = B:19 VAR: h2_to_2hi DATATYPE: BYTE4,
B:33 = U3:OUT:1 INSTR_LOG:1|d3_first#|d3_second#||1|0 VAR: d3_first DATATYPE: HALF2,
RF:8:IN:0:REG:2 = B:33 STAGE:1 VAR: d3_first DATATYPE: HALF2,
B:32 = U3:OUT:0 INSTR_LOG:1|d3_first#|d3_second#||1|0 VAR: d3_second DATATYPE: HALF2,
RF:4:IN:0:REG:2 = B:32 STAGE:1 VAR: d3_second DATATYPE: HALF2,
B:30 = U1:OUT:0 INSTR_LOG:2|diffy#4#||0 VAR: diffy#4 DATATYPE: HALF2,
RF:10:IN:0:REG:1 = B:30 STAGE:1 VAR: diffy#4 DATATYPE: HALF2,
B:38 = RF:18:OUT:1:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U7:IN:2 = B:38 VAR: hw_const#0 DATATYPE: ANYINT,
B:8 = RF:2:OUT:0:REG:1 VAR: currhi#2 DATATYPE: HALF2,
U7:IN:0 = B:8 VAR: currhi#2 DATATYPE: HALF2,
B:27 = U7:OUT:0 INSTR_LOG:1|currhi#2#||0 VAR: currhi#2 DATATYPE: HALF2,
RF:5:IN:0:REG:2 = B:27 STAGE:1 VAR: currhi#2 DATATYPE: HALF2,
// IN:ADDER_2: ( tmp#47 ) = OR( d0_first == UNITRF_1_3[3], d2_first == UNITRF_0_4[2] )
// OUT:ADDER_2: OR => ( tmp#47 == UNITRF_0_0[1] )
// IN:SP_SCHED_WRITE_0: ( buf1 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#46 == UNITRF_0_0[1] )
// IN:ADDER_0: ( diffy#12 ) = ISUB16( currlo#6 == UNITRF_0_2[1], reflo#6 == UNITRF_1_1[1] )
// IN:MULTIPLIER_0: ( d3_first, d3_second ) = SHUFFLED( diffy#9 == MULRF_0_0[1], h2_to_2hi == MULRF_1_0[1] )
// OUT:MULTIPLIER_0: SHUFFLED => ( d3_first == UNITRF_1_2[2], d3_second == UNITRF_0_3[2] )
// OUT:SP_SCHED_WRITE_0: SPWRITE => ( buf3 == SP_SCHED_RF_0[8] )
// OUT:ADDER_1: ISUB16 => ( diffy#4 == MULRF_0_0[1] )
// IN:COMM_SCHED_0: ( currhi#2 ) = NSELECT( hw_const#0 == CCRF_0[0], currhi#2 == UNITRF_0_1[1] )
// OUT:COMM_SCHED_0: NSELECT => ( currhi#2 == UNITRF_0_4[2] )
DEAD_REGS: { };
instr: 26
MC: OP: NONE LINE:-1,
U1: OP: OR LINE:212 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:212
U6: OP: SPWRITE LINE:211 SP_BASE:1 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:211
U6: OP: SPREAD_WT LINE:300 SP_BASE:8 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:300
U2: OP: ISUB16 LINE:190 STAGE:1, // D:\working\im_apps\h264\diff_kc.i:190
B:15 = RF:8:OUT:0:REG:1 VAR: d1_second DATATYPE: HALF2,
U1:IN:1 = B:15 VAR: d1_second DATATYPE: HALF2,
B:14 = RF:4:OUT:0:REG:2 VAR: d3_second DATATYPE: HALF2,
U1:IN:0 = B:14 VAR: d3_second DATATYPE: HALF2,
B:30 = U1:OUT:0 INSTR_LOG:1|tmp#48#||0 VAR: tmp#48 DATATYPE: UNDEFINED,
RF:1:IN:0:REG:1 = B:30 STAGE:1 VAR: tmp#48 DATATYPE: UNDEFINED,
B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
B:6 = RF:1:OUT:0:REG:1 VAR: tmp#47 DATATYPE: UNDEFINED,
U6:IN:1 = B:6 VAR: tmp#47 DATATYPE: UNDEFINED,
B:29 = U0:OUT:0 INSTR_LOG:2|diffy#12#||0 VAR: diffy#12 DATATYPE: HALF2,
RF:11:IN:0:REG:1 = B:29 STAGE:1 VAR: diffy#12 DATATYPE: HALF2,
B:5 = RF:16:OUT:0:REG:4 VAR: idx4 DATATYPE: INT,
U6:IN:0 = B:5 VAR: idx4 DATATYPE: INT,
B:16 = RF:5:OUT:0:REG:2 VAR: currhi#2 DATATYPE: HALF2,
U2:IN:0 = B:16 VAR: currhi#2 DATATYPE: HALF2,
B:17 = RF:9:OUT:0:REG:1 VAR: refhi#2 DATATYPE: HALF2,
U2:IN:1 = B:17 VAR: refhi#2 DATATYPE: HALF2,
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