📄 me_fast_jitter2_kc.uc
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RF:20:IN:0:REG:1 = B:51 STAGE:-1 VAR: vld_motions_in#115 DATATYPE: UNDEFINED,
// IN:COMM_SCHED_0: ( const#8 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#8 == PERMRF_0[0] )
// OUT:COMM_SCHED_0: SELECT => ( const#8 == UNITRF_1_3[2], const#8 == UNITRF_0_3[1] )
// IN:ADDER_1: ( const#2 ) = SHIFT32( const#1 == UNITRF_0_3[1], hw_const#1 == UNITRF_1_2[0] )
// OUT:ADDER_1: SHIFT32 => ( const#2 == MULRF_0_1[1], const#2 == UNITRF_1_2[3], const#2 == UNITRF_1_1[1], const#2 == UNITRF_0_4[1] )
// IN:ADDER_2: ( const#-2 ) = NOT( const#1 == UNITRF_0_4[1] )
// OUT:ADDER_2: NOT => ( const#-2 == UNITRF_0_2[1], const#-2 == MULRF_1_1[3], const#-2 == UNITRF_1_0[3] )
// OUT:JUKEBOX_SCHED_0: INIT_COSTATE => ( jb_motions_out#117 == JBRF_0[4] )
// OUT:INOUT_4: DATA_IN => ( tmp#116 == UNITRF_0_0[1] )
// OUT:VALID_SCHED_0: INIT_VALID => ( vld_motions_in#115 == VALIDRF_0[1] )
DEAD_REGS: { };
instr: 11
MC: OP: SYNCH LINE:40,
U1: OP: SHIFT32 LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
U0: OP: NOT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
B:14 = RF:4:OUT:0:REG:1 VAR: const#8 DATATYPE: ANYINT,
U1:IN:0 = B:14 VAR: const#8 DATATYPE: ANYINT,
B:15 = RF:8:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: hw_const#1 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|const#16#||0 VAR: const#16 DATATYPE: ANYINT,
RF:4:IN:0:REG:1 = B:30 STAGE:-1 VAR: const#16 DATATYPE: ANYINT,
RF:7:IN:0:REG:2 = B:30 STAGE:-1 VAR: const#16 DATATYPE: ANYINT,
RF:14:IN:0:REG:2 = B:30 STAGE:-1 VAR: const#16 DATATYPE: ANYINT,
RF:3:IN:0:REG:3 = B:30 STAGE:-1 VAR: const#16 DATATYPE: ANYINT,
RF:9:IN:0:REG:1 = B:30 STAGE:-1 VAR: const#16 DATATYPE: ANYINT,
B:12 = RF:3:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U0:IN:0 = B:12 VAR: hw_const#0 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|const#-1#||0 VAR: const#-1 DATATYPE: ANYINT,
RF:5:IN:0:REG:2 = B:29 STAGE:-1 VAR: const#-1 DATATYPE: ANYINT,
RF:8:IN:0:REG:2 = B:29 STAGE:-1 VAR: const#-1 DATATYPE: ANYINT,
// IN:ADDER_1: ( const#16 ) = SHIFT32( const#8 == UNITRF_0_3[1], hw_const#1 == UNITRF_1_2[0] )
// OUT:ADDER_1: SHIFT32 => ( const#16 == UNITRF_0_3[1], const#16 == UNITRF_1_1[2], const#16 == UNITRF_CID_0[2], const#16 == UNITRF_0_2[3], const#16 == UNITRF_1_3[1] )
// IN:ADDER_0: ( const#-1 ) = NOT( hw_const#0 == UNITRF_0_2[0] )
// OUT:ADDER_0: NOT => ( const#-1 == UNITRF_0_4[2], const#-1 == UNITRF_1_2[2] )
DEAD_REGS: { };
instr: 12
MC: OP: NONE LINE:-1,
U1: OP: NOT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
U2: OP: SHIFT32 LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
U0: OP: SHIFT32 LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
B:14 = RF:4:OUT:0:REG:1 VAR: const#16 DATATYPE: ANYINT,
U1:IN:0 = B:14 VAR: const#16 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|const#-17#||0 VAR: const#-17 DATATYPE: ANYINT,
RF:5:IN:0:REG:2 = B:30 STAGE:-1 VAR: const#-17 DATATYPE: ANYINT,
B:16 = RF:5:OUT:0:REG:2 VAR: const#-1 DATATYPE: ANYINT,
U2:IN:0 = B:16 VAR: const#-1 DATATYPE: ANYINT,
B:17 = RF:9:OUT:0:REG:2 VAR: const#8 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#8 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|const#-256#||0 VAR: const#-256 DATATYPE: ANYINT,
RF:3:IN:0:REG:1 = B:31 STAGE:-1 VAR: const#-256 DATATYPE: ANYINT,
B:12 = RF:3:OUT:0:REG:1 VAR: const#-2 DATATYPE: ANYINT,
U0:IN:0 = B:12 VAR: const#-2 DATATYPE: ANYINT,
B:13 = RF:7:OUT:0:REG:1 VAR: const#2 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#2 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|const#-8#||0 VAR: const#-8 DATATYPE: ANYINT,
RF:9:IN:0:REG:2 = B:29 STAGE:-1 VAR: const#-8 DATATYPE: ANYINT,
RF:8:IN:0:REG:5 = B:29 STAGE:-1 VAR: const#-8 DATATYPE: ANYINT,
// IN:ADDER_1: ( const#-17 ) = NOT( const#16 == UNITRF_0_3[1] )
// OUT:ADDER_1: NOT => ( const#-17 == UNITRF_0_4[2] )
// IN:ADDER_2: ( const#-256 ) = SHIFT32( const#-1 == UNITRF_0_4[2], const#8 == UNITRF_1_3[2] )
// OUT:ADDER_2: SHIFT32 => ( const#-256 == UNITRF_0_2[1] )
// IN:ADDER_0: ( const#-8 ) = SHIFT32( const#-2 == UNITRF_0_2[1], const#2 == UNITRF_1_1[1] )
// OUT:ADDER_0: SHIFT32 => ( const#-8 == UNITRF_1_3[2], const#-8 == UNITRF_1_2[5] )
DEAD_REGS: { };
instr: 13
MC: OP: NONE LINE:-1 UCRF_RD:1,
U2: OP: AND LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
U3: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
U7: OP: COMMUCDATA LINE:41 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:41
U0: OP: NOT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
B:16 = RF:5:OUT:0:REG:2 VAR: const#-17 DATATYPE: ANYINT,
U2:IN:0 = B:16 VAR: const#-17 DATATYPE: ANYINT,
B:17 = RF:9:OUT:0:REG:2 VAR: const#-8 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#-8 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|const#-24#||0 VAR: const#-24 DATATYPE: ANYINT,
RF:7:IN:0:REG:3 = B:31 STAGE:-1 VAR: const#-24 DATATYPE: ANYINT,
B:43 = RF:18:OUT:6:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U3:IN:2 = B:43 VAR: hw_const#0 DATATYPE: ANYINT,
B:19 = RF:12:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
U3:IN:1 = B:19 VAR: hw_const#1 DATATYPE: ANYINT,
B:33 = U3:OUT:1 INSTR_LOG:1|const#1#||1 VAR: const#1 DATATYPE: ANYINT,
RF:4:IN:0:REG:2 = B:33 STAGE:-1 VAR: const#1 DATATYPE: ANYINT,
B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
B:27 = U7:OUT:0 INSTR_LOG:1|margin#||0 VAR: margin DATATYPE: INT,
RF:8:IN:0:REG:4 = B:27 STAGE:-1 VAR: margin DATATYPE: INT,
RF:10:IN:0:REG:3 = B:27 STAGE:-1 VAR: margin DATATYPE: INT,
RF:5:IN:0:REG:2 = B:27 STAGE:-1 VAR: margin DATATYPE: INT,
RF:3:IN:0:REG:1 = B:27 STAGE:-1 VAR: margin DATATYPE: INT,
B:12 = RF:3:OUT:0:REG:1 VAR: const#-256 DATATYPE: ANYINT,
U0:IN:0 = B:12 VAR: const#-256 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|const#255#||0 VAR: const#255 DATATYPE: ANYINT,
RF:6:IN:0:REG:2 = B:29 STAGE:-1 VAR: const#255 DATATYPE: ANYINT,
RF:9:IN:0:REG:3 = B:29 STAGE:-1 VAR: const#255 DATATYPE: ANYINT,
RF:11:IN:0:REG:2 = B:29 STAGE:-1 VAR: const#255 DATATYPE: ANYINT,
// IN:ADDER_2: ( const#-24 ) = AND( const#-17 == UNITRF_0_4[2], const#-8 == UNITRF_1_3[2] )
// OUT:ADDER_2: AND => ( const#-24 == UNITRF_1_1[3] )
// IN:MULTIPLIER_0: ( const#1 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#1 == MULRF_1_0[0] )
// OUT:MULTIPLIER_0: SELECT => ( const#1 == UNITRF_0_3[2] )
// IN:COMM_SCHED_0: ( margin ) = COMMUCDATA( hw_const#8 == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_margin == UCRF_0[1] )
// OUT:COMM_SCHED_0: COMMUCDATA => ( margin == UNITRF_1_2[4], margin == MULRF_0_0[3], margin == UNITRF_0_4[2], margin == UNITRF_0_2[1] )
// IN:ADDER_0: ( const#255 ) = NOT( const#-256 == UNITRF_0_2[1] )
// OUT:ADDER_0: NOT => ( const#255 == UNITRF_1_0[2], const#255 == UNITRF_1_3[3], const#255 == MULRF_0_1[2] )
DEAD_REGS: { };
instr: 14
MC: OP: NONE LINE:-1 UCRF_RD:2,
U0: OP: SHIFT32 LINE:48 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:48
U7: OP: COMMUCDATA LINE:42 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:42
U1: OP: SHIFT32 LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
B:12 = RF:3:OUT:0:REG:1 VAR: margin DATATYPE: INT,
U0:IN:0 = B:12 VAR: margin DATATYPE: INT,
B:13 = RF:7:OUT:0:REG:3 VAR: const#-24 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#-24 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|tmp#120#||0 VAR: tmp#120 DATATYPE: INT,
RF:5:IN:0:REG:3 = B:29 STAGE:-1 VAR: tmp#120 DATATYPE: INT,
B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
B:27 = U7:OUT:0 INSTR_LOG:1|mblks#||0 VAR: mblks DATATYPE: INT,
RF:4:IN:0:REG:2 = B:27 STAGE:-1 VAR: mblks DATATYPE: INT,
RF:10:IN:0:REG:2 = B:27 STAGE:-1 VAR: mblks DATATYPE: INT,
B:14 = RF:4:OUT:0:REG:2 VAR: const#1 DATATYPE: ANYINT,
U1:IN:0 = B:14 VAR: const#1 DATATYPE: ANYINT,
B:15 = RF:8:OUT:0:REG:3 VAR: const#2 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: const#2 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|const#4#||0 VAR: const#4 DATATYPE: ANYINT,
RF:9:IN:0:REG:5 = B:30 STAGE:-1 VAR: const#4 DATATYPE: ANYINT,
RF:7:IN:0:REG:3 = B:30 STAGE:-1 VAR: const#4 DATATYPE: ANYINT,
RF:8:IN:0:REG:3 = B:30 STAGE:-1 VAR: const#4 DATATYPE: ANYINT,
// IN:ADDER_0: ( tmp#120 ) = SHIFT32( margin == UNITRF_0_2[1], const#-24 == UNITRF_1_1[3] )
// OUT:ADDER_0: SHIFT32 => ( tmp#120 == UNITRF_0_4[3] )
// IN:COMM_SCHED_0: ( mblks ) = COMMUCDATA( hw_const#8 == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_mblks == UCRF_0[2] )
// OUT:COMM_SCHED_0: COMMUCDATA => ( mblks == UNITRF_0_3[2], mblks == MULRF_0_0[2] )
// IN:ADDER_1: ( const#4 ) = SHIFT32( const#1 == UNITRF_0_3[2], const#2 == UNITRF_1_2[3] )
// OUT:ADDER_1: SHIFT32 => ( const#4 == UNITRF_1_3[5], const#4 == UNITRF_1_1[3], const#4 == UNITRF_1_2[3] )
DEAD_REGS: { };
instr: 15
MC: OP: NONE LINE:-1,
U2: OP: AND LINE:48 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:48
U1: OP: SHIFT32 LINE:76 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:76
U0: OP: NOT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
B:16 = RF:5:OUT:0:REG:3 VAR: tmp#120 DATATYPE: INT,
U2:IN:0 = B:16 VAR: tmp#120 DATATYPE: INT,
B:17 = RF:9:OUT:0:REG:3 VAR: const#255 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#255 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|right_margin#||0 VAR: right_margin DATATYPE: INT,
RF:4:IN:0:REG:2 = B:31 STAGE:-1 VAR: right_margin DATATYPE: INT,
B:14 = RF:4:OUT:0:REG:2 VAR: mblks DATATYPE: INT,
U1:IN:0 = B:14 VAR: mblks DATATYPE: INT,
B:15 = RF:8:OUT:0:REG:3 VAR: const#4 DATATYPE: ANYINT,
U1:IN:1 = B:15 VAR: const#4 DATATYPE: ANYINT,
B:30 = U1:OUT:0 INSTR_LOG:1|tmp#129#||0 VAR: tmp#129 DATATYPE: INT,
RF:8:IN:0:REG:3 = B:30 STAGE:-1 VAR: tmp#129 DATATYPE: INT,
B:12 = RF:3:OUT:0:REG:2 VAR: const#8 DATATYPE: ANYINT,
U0:IN:0 = B:12 VAR: const#8 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|const#-9#||0 VAR: const#-9 DATATYPE: ANYINT,
RF:5:IN:0:REG:3 = B:29 STAGE:-1 VAR: const#-9 DATATYPE: ANYINT,
// IN:ADDER_2: ( right_margin ) = AND( tmp#120 == UNITRF_0_4[3], const#255 == UNITRF_1_3[3] )
// OUT:ADDER_2: AND => ( right_margin == UNITRF_0_3[2] )
// IN:ADDER_1: ( tmp#129 ) = SHIFT32( mblks == UNITRF_0_3[2], const#4 == UNITRF_1_2[3] )
// OUT:ADDER_1: SHIFT32 => ( tmp#129 == UNITRF_1_2[3] )
// IN:ADDER_0: ( const#-9 ) = NOT( const#8 == UNITRF_0_2[2] )
// OUT:ADDER_0: NOT => ( const#-9 == UNITRF_0_4[3] )
DEAD_REGS: { };
instr: 16
MC: OP: NONE LINE:-1,
U1: OP: IADD32 LINE:76 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:76
U2: OP: AND LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
B:15 = RF:8:OUT:0:REG:3 VAR: tmp#129 DATATYPE: INT,
U1:IN:1 = B:15 VAR: tmp#129 DATATYPE: INT,
B:14 = RF:4:OUT:0:REG:2 VAR: right_margin DATATYPE: INT,
U1:IN:0 = B:14 VAR: right_margin DATATYPE: INT,
B:16 = RF:5:OUT:0:REG:3 VAR: const#-9 DATATYPE: ANYINT,
U2:IN:0 = B:16 VAR: const#-9 DATATYPE: ANYINT,
B:17 = RF:9:OUT:0:REG:2 VAR: const#-8 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#-8 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|const#-16#||0 VAR: const#-16 DATATYPE: ANYINT,
RF:9:IN:0:REG:2 = B:31 STAGE:-1 VAR: const#-16 DATATYPE: ANYINT,
RF:3:IN:0:REG:1 = B:31 STAGE:-1 VAR: const#-16 DATATYPE: ANYINT,
RF:8:IN:0:REG:3 = B:31 STAGE:-1 VAR: const#-16 DATATYPE: ANYINT,
RF:12:IN:0:REG:4 = B:31 STAGE:-1 VAR: const#-16 DATATYPE: ANYINT,
// IN:ADDER_1: ( tmp#130 ) = IADD32( tmp#129 == UNITRF_1_2[3], right_margin == UNITRF_0_3[2] )
// IN:ADDER_2: ( const#-16 ) = AND( const#-9 == UNITRF_0_4[3], const#-8 == UNITRF_1_3[2] )
// OUT:ADDER_2: AND => ( const#-16 == UNITRF_1_3[2], const#-16 == UNITRF_0_2[1], const#-16 == UNITRF_1_2[3], const#-16 == MULRF_1_0[4] )
DEAD_REGS: { };
instr: 17
MC: OP: NONE LINE:-1,
U2: OP: SHIFT32 LINE:47 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:47
U4: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
U0: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter2_kc.i:-1
B:30 = U1:OUT:0 INSTR_LOG:2|tmp#130#||0 VAR: tmp#130 DATATYPE: INT,
RF:3:IN:0:REG:2 = B:30 STAGE:-1 VAR: tmp#130 DATATYPE: INT,
B:16 = RF:5:OUT:0:REG:2 VAR: margin DATATYPE: INT,
U2:IN:0 = B:16 VAR: margin DATATYPE: INT,
B:17 = RF:9:OUT:0:REG:2 VAR: const#-16 DATATYPE: ANYINT,
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