📄 idxgen_kc.uc
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B:14 = RF:4:OUT:0:REG:3 VAR: const#5 DATATYPE: ANYINT,
U1:IN:0 = B:14 VAR: const#5 DATATYPE: ANYINT,
B:15 = RF:8:OUT:0:REG:5 VAR: bottom_margin DATATYPE: INT,
U1:IN:1 = B:15 VAR: bottom_margin DATATYPE: INT,
// IN:COMM_SCHED_0: ( const#8 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#8 == PERMRF_0[0] )
// OUT:COMM_SCHED_0: SELECT => ( const#8 == UNITRF_0_3[3] )
// IN:ADDER_0: ( tmp#38 ) = ILT32( const#7 == UNITRF_0_2[3], bottom_margin == UNITRF_1_1[3] )
// IN:ADDER_2: ( tmp#35 ) = ILT32( const#6 == UNITRF_0_4[4], bottom_margin == UNITRF_1_3[2] )
// IN:ADDER_1: ( tmp#32 ) = ILT32( const#5 == UNITRF_0_3[3], bottom_margin == UNITRF_1_2[5] )
DEAD_REGS: { };
instr: 16
MC: OP: NONE LINE:-1,
U7: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
U1: OP: ILT32 LINE:56 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:56
B:38 = RF:18:OUT:1:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U7:IN:2 = B:38 VAR: hw_const#0 DATATYPE: ANYINT,
B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
B:27 = U7:OUT:0 INSTR_LOG:1|const#8#||0 VAR: const#8 DATATYPE: ANYINT,
RF:5:IN:0:REG:4 = B:27 STAGE:-1 VAR: const#8 DATATYPE: ANYINT,
B:14 = RF:4:OUT:0:REG:3 VAR: const#8 DATATYPE: ANYINT,
U1:IN:0 = B:14 VAR: const#8 DATATYPE: ANYINT,
B:15 = RF:8:OUT:0:REG:5 VAR: bottom_margin DATATYPE: INT,
U1:IN:1 = B:15 VAR: bottom_margin DATATYPE: INT,
B:45 = U0:OUT:0 INSTR_LOG:2|tmp#38#||0 VAR: tmp#38 DATATYPE: CC,
RF:18:IN:0:REG:4 = B:45 STAGE:-1 VAR: tmp#38 DATATYPE: CC,
B:47 = U2:OUT:0 INSTR_LOG:2|tmp#35#||0 VAR: tmp#35 DATATYPE: CC,
RF:18:IN:1:REG:7 = B:47 STAGE:-1 VAR: tmp#35 DATATYPE: CC,
B:30 = U1:OUT:0 INSTR_LOG:2|tmp#32#||0 VAR: tmp#32 DATATYPE: CC,
RF:3:IN:0:REG:3 = B:30 STAGE:-1 VAR: tmp#32 DATATYPE: CC,
// IN:COMM_SCHED_0: ( const#8 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#8 == PERMRF_0[0] )
// OUT:COMM_SCHED_0: SELECT => ( const#8 == UNITRF_0_4[4] )
// IN:ADDER_1: ( tmp#41 ) = ILT32( const#8 == UNITRF_0_3[3], bottom_margin == UNITRF_1_2[5] )
// OUT:ADDER_0: ILT32 => ( tmp#38 == CCRF_0[4] )
// OUT:ADDER_2: ILT32 => ( tmp#35 == CCRF_0[7] )
// OUT:ADDER_1: ILT32 => ( tmp#32 == UNITRF_0_2[3] )
DEAD_REGS: { };
instr: 17
MC: OP: NONE LINE:-1,
U0: OP: AND LINE:36 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:36
U2: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
U1: OP: ILT32 LINE:57 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:57
B:13 = RF:7:OUT:0:REG:5 VAR: width DATATYPE: INT,
U0:IN:1 = B:13 VAR: width DATATYPE: INT,
B:12 = RF:3:OUT:0:REG:2 VAR: const#15 DATATYPE: ANYINT,
U0:IN:0 = B:12 VAR: const#15 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|right_margin#||0 VAR: right_margin DATATYPE: INT,
RF:8:IN:0:REG:2 = B:29 STAGE:-1 VAR: right_margin DATATYPE: INT,
RF:11:IN:0:REG:1 = B:29 STAGE:-1 VAR: right_margin DATATYPE: INT,
B:16 = RF:5:OUT:0:REG:4 VAR: const#8 DATATYPE: ANYINT,
U2:IN:0 = B:16 VAR: const#8 DATATYPE: ANYINT,
B:17 = RF:9:OUT:0:REG:3 VAR: const#2 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: const#2 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|const#10#||0 VAR: const#10 DATATYPE: ANYINT,
RF:3:IN:0:REG:2 = B:31 STAGE:-1 VAR: const#10 DATATYPE: ANYINT,
RF:4:IN:0:REG:2 = B:31 STAGE:-1 VAR: const#10 DATATYPE: ANYINT,
B:14 = RF:4:OUT:0:REG:2 VAR: const#9 DATATYPE: ANYINT,
U1:IN:0 = B:14 VAR: const#9 DATATYPE: ANYINT,
B:15 = RF:8:OUT:0:REG:5 VAR: bottom_margin DATATYPE: INT,
U1:IN:1 = B:15 VAR: bottom_margin DATATYPE: INT,
B:46 = U1:OUT:0 INSTR_LOG:2|tmp#41#||0 VAR: tmp#41 DATATYPE: CC,
RF:18:IN:0:REG:5 = B:46 STAGE:-1 VAR: tmp#41 DATATYPE: CC,
// IN:ADDER_0: ( right_margin ) = AND( width == UNITRF_1_1[5], const#15 == UNITRF_0_2[2] )
// OUT:ADDER_0: AND => ( right_margin == UNITRF_1_2[2], right_margin == MULRF_0_1[1] )
// IN:ADDER_2: ( const#10 ) = OR( const#8 == UNITRF_0_4[4], const#2 == UNITRF_1_3[3] )
// OUT:ADDER_2: OR => ( const#10 == UNITRF_0_2[2], const#10 == UNITRF_0_3[2] )
// IN:ADDER_1: ( tmp#44 ) = ILT32( const#9 == UNITRF_0_3[2], bottom_margin == UNITRF_1_2[5] )
// OUT:ADDER_1: ILT32 => ( tmp#41 == CCRF_0[5] )
DEAD_REGS: { };
instr: 18
MC: OP: NONE LINE:-1,
U1: OP: ILT32 LINE:37 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:37
U0: OP: IEQ32 LINE:35 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:35
U2: OP: IEQ32 LINE:35 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:35
B:15 = RF:8:OUT:0:REG:2 VAR: right_margin DATATYPE: INT,
U1:IN:1 = B:15 VAR: right_margin DATATYPE: INT,
B:14 = RF:4:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U1:IN:0 = B:14 VAR: hw_const#0 DATATYPE: ANYINT,
B:13 = RF:7:OUT:0:REG:2 VAR: type DATATYPE: INT,
U0:IN:1 = B:13 VAR: type DATATYPE: INT,
B:12 = RF:3:OUT:0:REG:1 VAR: const#3 DATATYPE: ANYINT,
U0:IN:0 = B:12 VAR: const#3 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|tmp#2#||0 VAR: tmp#2 DATATYPE: INT,
RF:5:IN:0:REG:2 = B:29 STAGE:-1 VAR: tmp#2 DATATYPE: INT,
B:16 = RF:5:OUT:0:REG:2 VAR: type DATATYPE: INT,
U2:IN:0 = B:16 VAR: type DATATYPE: INT,
B:17 = RF:9:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
U2:IN:1 = B:17 VAR: hw_const#1 DATATYPE: ANYINT,
B:31 = U2:OUT:0 INSTR_LOG:1|tmp#1#||0 VAR: tmp#1 DATATYPE: INT,
RF:9:IN:0:REG:3 = B:31 STAGE:-1 VAR: tmp#1 DATATYPE: INT,
B:46 = U1:OUT:0 INSTR_LOG:2|tmp#44#||0 VAR: tmp#44 DATATYPE: CC,
RF:18:IN:0:REG:6 = B:46 STAGE:-1 VAR: tmp#44 DATATYPE: CC,
// IN:ADDER_1: ( tmp#3 ) = ILT32( right_margin == UNITRF_1_2[2], hw_const#0 == UNITRF_0_3[0] )
// IN:ADDER_0: ( tmp#2 ) = IEQ32( type == UNITRF_1_1[2], const#3 == UNITRF_0_2[1] )
// OUT:ADDER_0: IEQ32 => ( tmp#2 == UNITRF_0_4[2] )
// IN:ADDER_2: ( tmp#1 ) = IEQ32( type == UNITRF_0_4[2], hw_const#1 == UNITRF_1_3[0] )
// OUT:ADDER_2: IEQ32 => ( tmp#1 == UNITRF_1_3[3] )
// OUT:ADDER_1: ILT32 => ( tmp#44 == CCRF_0[6] )
DEAD_REGS: { };
instr: 19
MC: OP: NONE LINE:-1,
U2: OP: OR LINE:35 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:35
U1: OP: ILT32 LINE:58 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:58
U0: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
U4: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
U5: OP: NSELECT LINE:28 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:28
B:30 = U1:OUT:0 INSTR_LOG:2|tmp#3#||0 VAR: tmp#3 DATATYPE: INT,
RF:5:IN:0:REG:2 = B:30 STAGE:-1 VAR: tmp#3 DATATYPE: INT,
B:17 = RF:9:OUT:0:REG:3 VAR: tmp#1 DATATYPE: INT,
U2:IN:1 = B:17 VAR: tmp#1 DATATYPE: INT,
B:16 = RF:5:OUT:0:REG:2 VAR: tmp#2 DATATYPE: INT,
U2:IN:0 = B:16 VAR: tmp#2 DATATYPE: INT,
B:31 = U2:OUT:0 INSTR_LOG:1|right_side#||0 VAR: right_side DATATYPE: INT,
RF:9:IN:0:REG:3 = B:31 STAGE:-1 VAR: right_side DATATYPE: INT,
B:14 = RF:4:OUT:0:REG:2 VAR: const#10 DATATYPE: ANYINT,
U1:IN:0 = B:14 VAR: const#10 DATATYPE: ANYINT,
B:15 = RF:8:OUT:0:REG:5 VAR: bottom_margin DATATYPE: INT,
U1:IN:1 = B:15 VAR: bottom_margin DATATYPE: INT,
B:40 = RF:18:OUT:3:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U0:IN:2 = B:40 VAR: hw_const#0 DATATYPE: ANYINT,
B:12 = RF:3:OUT:0:REG:3 VAR: tmp#32 DATATYPE: CC,
U0:IN:0 = B:12 VAR: tmp#32 DATATYPE: CC,
B:45 = U0:OUT:0 INSTR_LOG:1|tmp#32#||0 VAR: tmp#32 DATATYPE: CC,
RF:18:IN:0:REG:9 = B:45 STAGE:-1 VAR: tmp#32 DATATYPE: CC,
B:44 = RF:18:OUT:7:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U4:IN:2 = B:44 VAR: hw_const#0 DATATYPE: ANYINT,
B:20 = RF:11:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U4:IN:0 = B:20 VAR: hw_const#0 DATATYPE: ANYINT,
B:35 = U4:OUT:1 INSTR_LOG:1|const#0#||1 VAR: const#0 DATATYPE: ANYINT,
RF:6:IN:0:REG:1 = B:35 STAGE:-1 VAR: const#0 DATATYPE: ANYINT,
B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
B:10 = RF:6:OUT:0:REG:1 VAR: params2_second DATATYPE: INT,
U5:IN:0 = B:10 VAR: params2_second DATATYPE: INT,
B:28 = U5:OUT:0 INSTR_LOG:1|cnt#||0 VAR: cnt DATATYPE: INT,
RF:2:IN:0:REG:1 = B:28 STAGE:-1 VAR: cnt DATATYPE: INT,
RF:3:IN:0:REG:1 = B:28 STAGE:-1 VAR: cnt DATATYPE: INT,
// OUT:ADDER_1: ILT32 => ( tmp#3 == UNITRF_0_4[2] )
// IN:ADDER_2: ( right_side ) = OR( tmp#1 == UNITRF_1_3[3], tmp#2 == UNITRF_0_4[2] )
// OUT:ADDER_2: OR => ( right_side == UNITRF_1_3[3] )
// IN:ADDER_1: ( tmp#47 ) = ILT32( const#10 == UNITRF_0_3[2], bottom_margin == UNITRF_1_2[5] )
// IN:ADDER_0: ( tmp#32 ) = NSELECT( hw_const#0 == CCRF_0[0], tmp#32 == UNITRF_0_2[3] )
// OUT:ADDER_0: NSELECT => ( tmp#32 == CCRF_0[9] )
// IN:MULTIPLIER_1: ( const#0 ) = NSELECT( hw_const#0 == CCRF_0[0], hw_const#0 == MULRF_0_1[0] )
// OUT:MULTIPLIER_1: NSELECT => ( const#0 == UNITRF_1_0[1] )
// IN:DIVIDER_0: ( cnt ) = NSELECT( hw_const#0 == CCRF_0[0], params2_second == UNITRF_1_0[1] )
// OUT:DIVIDER_0: NSELECT => ( cnt == UNITRF_0_1[1], cnt == UNITRF_0_2[1] )
DEAD_REGS: { };
instr: 20
MC: OP: NONE LINE:-1,
U2: OP: AND LINE:37 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:37
U7: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
U0: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
U4: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
U5: OP: NSELECT LINE:50 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:50
U3: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
B:16 = RF:5:OUT:0:REG:2 VAR: tmp#3 DATATYPE: INT,
U2:IN:0 = B:16 VAR: tmp#3 DATATYPE: INT,
B:17 = RF:9:OUT:0:REG:3 VAR: right_side DATATYPE: INT,
U2:IN:1 = B:17 VAR: right_side DATATYPE: INT,
B:47 = U2:OUT:0 INSTR_LOG:1|tmp#5#||0 VAR: tmp#5 DATATYPE: CC,
RF:18:IN:1:REG:10 = B:47 STAGE:-1 VAR: tmp#5 DATATYPE: CC,
B:38 = RF:18:OUT:1:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U7:IN:2 = B:38 VAR: hw_const#0 DATATYPE: ANYINT,
B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
B:27 = U7:OUT:0 INSTR_LOG:1|const#8#||0 VAR: const#8 DATATYPE: ANYINT,
RF:4:IN:0:REG:2 = B:27 STAGE:-1 VAR: const#8 DATATYPE: ANYINT,
B:12 = RF:3:OUT:0:REG:2 VAR: const#10 DATATYPE: ANYINT,
U0:IN:0 = B:12 VAR: const#10 DATATYPE: ANYINT,
B:13 = RF:7:OUT:0:REG:1 VAR: const#4 DATATYPE: ANYINT,
U0:IN:1 = B:13 VAR: const#4 DATATYPE: ANYINT,
B:29 = U0:OUT:0 INSTR_LOG:1|const#14#||0 VAR: const#14 DATATYPE: ANYINT,
RF:5:IN:0:REG:2 = B:29 STAGE:-1 VAR: const#14 DATATYPE: ANYINT,
B:46 = U1:OUT:0 INSTR_LOG:2|tmp#47#||0 VAR: tmp#47 DATATYPE: CC,
RF:18:IN:0:REG:8 = B:46 STAGE:-1 VAR: tmp#47 DATATYPE: CC,
B:44 = RF:18:OUT:7:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U4:IN:2 = B:44 VAR: hw_const#0 DATATYPE: ANYINT,
B:20 = RF:11:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U4:IN:0 = B:20 VAR: hw_const#0 DATATYPE: ANYINT,
B:35 = U4:OUT:1 INSTR_LOG:1|const#0#||1 VAR: const#0 DATATYPE: ANYINT,
RF:6:IN:0:REG:1 = B:35 STAGE:-1 VAR: const#0 DATATYPE: ANYINT,
B:39 = RF:18:OUT:2:REG:8 VAR: tmp#23 DATATYPE: CC,
U5:IN:2 = B:39 VAR: tmp#23 DATATYPE: CC,
B:11 = RF:14:OUT:0:REG:1 VAR: width DATATYPE: INT,
U5:IN:1 = B:11 VAR: width DATATYPE: INT,
B:10 = RF:6:OUT:0:REG:1 VAR: const#0 DATATYPE: ANYINT,
U5:IN:0 = B:10 VAR: const#0 DATATYPE: ANYINT,
B:28 = U5:OUT:0 INSTR_LOG:1|y#1#||0 VAR: y#1 DATATYPE: INT,
RF:8:IN:0:REG:2 = B:28 STAGE:-1 VAR: y#1 DATATYPE: INT,
B:43 = RF:18:OUT:6:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
U3:IN:2 = B:43 VAR: hw_const#0 DATATYPE: ANYINT,
B:18 = RF:10:OUT:0:REG:1 VAR: const#11 DATATYPE: ANYINT,
U3:IN:0 = B:18 VAR: const#11 DATATYPE: ANYINT,
B:33 = U3:OUT:1 INSTR_LOG:1|const#11#||1 VAR: const#11 DATATYPE: ANYINT,
RF:3:IN:0:REG:2 = B:33 STAGE:-1 VAR: const#11 DATATYPE: ANYINT,
// IN:ADDER_2: ( tmp#5 ) = AND( tmp#3 == UNITRF_0_4[2], right_side == UNITRF_1_3[3] )
// OUT:ADDER_2: AND => ( tmp#5 == CCRF_0[10] )
// IN:COMM_SCHED_0: ( const#8 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#8 == PERMRF_0[0] )
// OUT:COMM_SCHED_0: SELECT => ( const#8 == UNITRF_0_3[2] )
// IN:ADDER_0: ( const#14 ) = OR( const#10 == UNITRF_0_2[2], const#4 == UNITRF_1_1[1] )
// OUT:ADDER_0: OR => ( const#14 == UNITRF_0_4[2] )
// OUT:ADDER_1: ILT32 => ( tmp#47 == CCRF_0[8] )
// IN:MULTIPLIER_1: ( const#0 ) = NSELECT( hw_const#0 == CCRF_0[0], hw_const#0 == MULRF_0_1[0] )
// OUT:MULTIPLIER_1: NSELECT => ( const#0 == UNITRF_1_0[1] )
// IN:DIVIDER_0: ( y#1 ) = NSELECT( tmp#23 == CCRF_0[8], width == UNITRF_CID_0[1], const#0 == UNITRF_1_0[1] )
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