idxgen_kc.uc

来自「H.264完整的C语言代码和DCT的代码」· UC 代码 · 共 1,027 行 · 第 1/5 页

    U0:IN:0 = B:12 VAR: hw_const#0 DATATYPE: ANYINT,
    B:14 = RF:4:OUT:0:REG:5 VAR: type DATATYPE: INT,
    U1:IN:0 = B:14 VAR: type DATATYPE: INT,
    B:15 = RF:8:OUT:0:REG:2 VAR: const#2 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: const#2 DATATYPE: ANYINT,
    B:30 = U1:OUT:0 INSTR_LOG:1|tmp#13#||0 VAR: tmp#13 DATATYPE: INT,
    RF:5:IN:0:REG:4 = B:30 STAGE:-1 VAR: tmp#13 DATATYPE: INT,
    B:17 = RF:9:OUT:0:REG:2 VAR: type DATATYPE: INT,
    U2:IN:1 = B:17 VAR: type DATATYPE: INT,
    B:16 = RF:5:OUT:0:REG:4 VAR: const#3 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#3 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|tmp#14#||0 VAR: tmp#14 DATATYPE: INT,
    RF:9:IN:0:REG:2 = B:31 STAGE:-1 VAR: tmp#14 DATATYPE: INT,
    //  IN:ADDER_0: ( tmp#15 ) = ILT32( bottom_margin == UNITRF_1_1[3], hw_const#0 == UNITRF_0_2[0] )
    //  IN:ADDER_1: ( tmp#13 ) = IEQ32( type == UNITRF_0_3[5], const#2 == UNITRF_1_2[2] )
    // OUT:ADDER_1: IEQ32 => ( tmp#13 == UNITRF_0_4[4] )
    //  IN:ADDER_2: ( tmp#14 ) = IEQ32( type == UNITRF_1_3[2], const#3 == UNITRF_0_4[4] )
    // OUT:ADDER_2: IEQ32 => ( tmp#14 == UNITRF_1_3[2] )
    DEAD_REGS: {  };
instr: 8
    MC: OP: NONE LINE:-1,
    U2: OP: OR LINE:45 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:45
    B:29 = U0:OUT:0 INSTR_LOG:2|tmp#15#||0 VAR: tmp#15 DATATYPE: INT,
    RF:4:IN:0:REG:5 = B:29 STAGE:-1 VAR: tmp#15 DATATYPE: INT,
    B:16 = RF:5:OUT:0:REG:4 VAR: tmp#13 DATATYPE: INT,
    U2:IN:0 = B:16 VAR: tmp#13 DATATYPE: INT,
    B:17 = RF:9:OUT:0:REG:2 VAR: tmp#14 DATATYPE: INT,
    U2:IN:1 = B:17 VAR: tmp#14 DATATYPE: INT,
    B:31 = U2:OUT:0 INSTR_LOG:1|bottom_row#||0 VAR: bottom_row DATATYPE: INT,
    RF:8:IN:0:REG:1 = B:31 STAGE:-1 VAR: bottom_row DATATYPE: INT,
    // OUT:ADDER_0: ILT32 => ( tmp#15 == UNITRF_0_3[5] )
    //  IN:ADDER_2: ( bottom_row ) = OR( tmp#13 == UNITRF_0_4[4], tmp#14 == UNITRF_1_3[2] )
    // OUT:ADDER_2: OR => ( bottom_row == UNITRF_1_2[1] )
    DEAD_REGS: {  };
instr: 9
    MC: OP: NONE LINE:-1,
    U1: OP: AND LINE:47 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:47
    U2: OP: SHIFT32 LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    B:14 = RF:4:OUT:0:REG:5 VAR: tmp#15 DATATYPE: INT,
    U1:IN:0 = B:14 VAR: tmp#15 DATATYPE: INT,
    B:15 = RF:8:OUT:0:REG:1 VAR: bottom_row DATATYPE: INT,
    U1:IN:1 = B:15 VAR: bottom_row DATATYPE: INT,
    B:46 = U1:OUT:0 INSTR_LOG:1|tmp#17#||0 VAR: tmp#17 DATATYPE: CC,
    RF:18:IN:0:REG:1 = B:46 STAGE:-1 VAR: tmp#17 DATATYPE: CC,
    B:16 = RF:5:OUT:0:REG:3 VAR: const#8 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#8 DATATYPE: ANYINT,
    B:17 = RF:9:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: hw_const#1 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|const#16#||0 VAR: const#16 DATATYPE: ANYINT,
    RF:13:IN:0:REG:3 = B:31 STAGE:-1 VAR: const#16 DATATYPE: ANYINT,
    RF:15:IN:0:REG:2 = B:31 STAGE:-1 VAR: const#16 DATATYPE: ANYINT,
    RF:8:IN:0:REG:1 = B:31 STAGE:-1 VAR: const#16 DATATYPE: ANYINT,
    //  IN:ADDER_1: ( tmp#17 ) = AND( tmp#15 == UNITRF_0_3[5], bottom_row == UNITRF_1_2[1] )
    // OUT:ADDER_1: AND => ( tmp#17 == CCRF_0[1] )
    //  IN:ADDER_2: ( const#16 ) = SHIFT32( const#8 == UNITRF_0_4[3], hw_const#1 == UNITRF_1_3[0] )
    // OUT:ADDER_2: SHIFT32 => ( const#16 == MULRF_1_1[3], const#16 == PERMRF_0[2], const#16 == UNITRF_1_2[1] )
    DEAD_REGS: {  };
instr: 10
    MC: OP: NONE LINE:-1,
    U3: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U7: OP: SELECT LINE:47 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:47
    B:43 = RF:18:OUT:6:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U3:IN:2 = B:43 VAR: hw_const#0 DATATYPE: ANYINT,
    B:19 = RF:12:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U3:IN:1 = B:19 VAR: hw_const#1 DATATYPE: ANYINT,
    B:33 = U3:OUT:1 INSTR_LOG:1|const#1#||1 VAR: const#1 DATATYPE: ANYINT,
    RF:5:IN:0:REG:3 = B:33 STAGE:-1 VAR: const#1 DATATYPE: ANYINT,
    B:38 = RF:18:OUT:1:REG:1 VAR: tmp#17 DATATYPE: CC,
    U7:IN:2 = B:38 VAR: tmp#17 DATATYPE: CC,
    B:8 = RF:2:OUT:0:REG:1 VAR: bottom_margin DATATYPE: INT,
    U7:IN:0 = B:8 VAR: bottom_margin DATATYPE: INT,
    B:9 = RF:15:OUT:0:REG:2 VAR: const#16 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: const#16 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|bottom_margin#||0 VAR: bottom_margin DATATYPE: INT,
    RF:9:IN:0:REG:2 = B:27 STAGE:-1 VAR: bottom_margin DATATYPE: INT,
    RF:7:IN:0:REG:3 = B:27 STAGE:-1 VAR: bottom_margin DATATYPE: INT,
    RF:8:IN:0:REG:5 = B:27 STAGE:-1 VAR: bottom_margin DATATYPE: INT,
    //  IN:MULTIPLIER_0: ( const#1 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#1 == MULRF_1_0[0] )
    // OUT:MULTIPLIER_0: SELECT => ( const#1 == UNITRF_0_4[3] )
    //  IN:COMM_SCHED_0: ( bottom_margin ) = SELECT( tmp#17 == CCRF_0[1], bottom_margin == UNITRF_0_1[1], const#16 == PERMRF_0[2] )
    // OUT:COMM_SCHED_0: SELECT => ( bottom_margin == UNITRF_1_3[2], bottom_margin == UNITRF_1_1[3], bottom_margin == UNITRF_1_2[5] )
    DEAD_REGS: {  };
instr: 11
    MC: OP: NONE LINE:-1,
    U0: OP: ILT32 LINE:50 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:50
    U2: OP: ILT32 LINE:49 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:49
    U5: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U7: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    B:12 = RF:3:OUT:0:REG:4 VAR: const#2 DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: const#2 DATATYPE: ANYINT,
    B:13 = RF:7:OUT:0:REG:3 VAR: bottom_margin DATATYPE: INT,
    U0:IN:1 = B:13 VAR: bottom_margin DATATYPE: INT,
    B:16 = RF:5:OUT:0:REG:3 VAR: const#1 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#1 DATATYPE: ANYINT,
    B:17 = RF:9:OUT:0:REG:2 VAR: bottom_margin DATATYPE: INT,
    U2:IN:1 = B:17 VAR: bottom_margin DATATYPE: INT,
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:11 = RF:14:OUT:0:REG:0 VAR: cluster#id DATATYPE: ANYINT,
    U5:IN:1 = B:11 VAR: cluster#id DATATYPE: ANYINT,
    B:28 = U5:OUT:0 INSTR_LOG:1|cluster#id#||0 VAR: cluster#id DATATYPE: ANYINT,
    RF:3:IN:0:REG:4 = B:28 STAGE:-1 VAR: cluster#id DATATYPE: ANYINT,
    B:38 = RF:18:OUT:1:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:2 = B:38 VAR: hw_const#0 DATATYPE: ANYINT,
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|const#8#||0 VAR: const#8 DATATYPE: ANYINT,
    RF:7:IN:0:REG:4 = B:27 STAGE:-1 VAR: const#8 DATATYPE: ANYINT,
    //  IN:ADDER_0: ( tmp#23 ) = ILT32( const#2 == UNITRF_0_2[4], bottom_margin == UNITRF_1_1[3] )
    //  IN:ADDER_2: ( tmp#20 ) = ILT32( const#1 == UNITRF_0_4[3], bottom_margin == UNITRF_1_3[2] )
    //  IN:DIVIDER_0: ( cluster#id ) = SELECT( hw_const#0 == CCRF_0[0], cluster#id == UNITRF_CID_0[0] )
    // OUT:DIVIDER_0: SELECT => ( cluster#id == UNITRF_0_2[4] )
    //  IN:COMM_SCHED_0: ( const#8 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#8 == PERMRF_0[0] )
    // OUT:COMM_SCHED_0: SELECT => ( const#8 == UNITRF_1_1[4] )
    DEAD_REGS: {  };
instr: 12
    MC: OP: NONE LINE:-1,
    U2: OP: ILT32 LINE:52 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:52
    U1: OP: ILT32 LINE:51 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:51
    U0: OP: IADD32 LINE:39 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:39
    B:16 = RF:5:OUT:0:REG:1 VAR: const#4 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#4 DATATYPE: ANYINT,
    B:17 = RF:9:OUT:0:REG:2 VAR: bottom_margin DATATYPE: INT,
    U2:IN:1 = B:17 VAR: bottom_margin DATATYPE: INT,
    B:14 = RF:4:OUT:0:REG:4 VAR: const#3 DATATYPE: ANYINT,
    U1:IN:0 = B:14 VAR: const#3 DATATYPE: ANYINT,
    B:15 = RF:8:OUT:0:REG:5 VAR: bottom_margin DATATYPE: INT,
    U1:IN:1 = B:15 VAR: bottom_margin DATATYPE: INT,
    B:45 = U0:OUT:0 INSTR_LOG:2|tmp#23#||0 VAR: tmp#23 DATATYPE: CC,
    RF:18:IN:0:REG:8 = B:45 STAGE:-1 VAR: tmp#23 DATATYPE: CC,
    B:47 = U2:OUT:0 INSTR_LOG:2|tmp#20#||0 VAR: tmp#20 DATATYPE: CC,
    RF:18:IN:1:REG:2 = B:47 STAGE:-1 VAR: tmp#20 DATATYPE: CC,
    B:12 = RF:3:OUT:0:REG:4 VAR: cluster#id DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: cluster#id DATATYPE: ANYINT,
    B:13 = RF:7:OUT:0:REG:4 VAR: const#8 DATATYPE: ANYINT,
    U0:IN:1 = B:13 VAR: const#8 DATATYPE: ANYINT,
    //  IN:ADDER_2: ( tmp#29 ) = ILT32( const#4 == UNITRF_0_4[1], bottom_margin == UNITRF_1_3[2] )
    //  IN:ADDER_1: ( tmp#26 ) = ILT32( const#3 == UNITRF_0_3[4], bottom_margin == UNITRF_1_2[5] )
    // OUT:ADDER_0: ILT32 => ( tmp#23 == CCRF_0[8] )
    // OUT:ADDER_2: ILT32 => ( tmp#20 == CCRF_0[2] )
    //  IN:ADDER_0: ( cid8 ) = IADD32( cluster#id == UNITRF_0_2[4], const#8 == UNITRF_1_1[4] )
    DEAD_REGS: {  };
instr: 13
    MC: OP: NONE LINE:-1,
    B:47 = U2:OUT:0 INSTR_LOG:2|tmp#29#||0 VAR: tmp#29 DATATYPE: CC,
    RF:18:IN:1:REG:1 = B:47 STAGE:-1 VAR: tmp#29 DATATYPE: CC,
    B:46 = U1:OUT:0 INSTR_LOG:2|tmp#26#||0 VAR: tmp#26 DATATYPE: CC,
    RF:18:IN:0:REG:3 = B:46 STAGE:-1 VAR: tmp#26 DATATYPE: CC,
    B:29 = U0:OUT:0 INSTR_LOG:2|cid8#||0 VAR: cid8 DATATYPE: INT,
    RF:5:IN:0:REG:3 = B:29 STAGE:-1 VAR: cid8 DATATYPE: INT,
    RF:15:IN:0:REG:2 = B:29 STAGE:-1 VAR: cid8 DATATYPE: INT,
    RF:13:IN:0:REG:1 = B:29 STAGE:-1 VAR: cid8 DATATYPE: INT,
    // OUT:ADDER_2: ILT32 => ( tmp#29 == CCRF_0[1] )
    // OUT:ADDER_1: ILT32 => ( tmp#26 == CCRF_0[3] )
    // OUT:ADDER_0: IADD32 => ( cid8 == UNITRF_0_4[3], cid8 == PERMRF_0[2], cid8 == MULRF_1_1[1] )
    DEAD_REGS: {  };
instr: 14
    MC: OP: NONE LINE:-1,
    U2: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U1: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U0: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    B:17 = RF:9:OUT:0:REG:4 VAR: const#3 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#3 DATATYPE: ANYINT,
    B:16 = RF:5:OUT:0:REG:1 VAR: const#4 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#4 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|const#7#||0 VAR: const#7 DATATYPE: ANYINT,
    RF:3:IN:0:REG:3 = B:31 STAGE:-1 VAR: const#7 DATATYPE: ANYINT,
    B:15 = RF:8:OUT:0:REG:2 VAR: const#2 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: const#2 DATATYPE: ANYINT,
    B:14 = RF:4:OUT:0:REG:3 VAR: const#4 DATATYPE: ANYINT,
    U1:IN:0 = B:14 VAR: const#4 DATATYPE: ANYINT,
    B:30 = U1:OUT:0 INSTR_LOG:1|const#6#||0 VAR: const#6 DATATYPE: ANYINT,
    RF:5:IN:0:REG:4 = B:30 STAGE:-1 VAR: const#6 DATATYPE: ANYINT,
    B:13 = RF:7:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U0:IN:1 = B:13 VAR: hw_const#1 DATATYPE: ANYINT,
    B:12 = RF:3:OUT:0:REG:3 VAR: const#4 DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: const#4 DATATYPE: ANYINT,
    B:29 = U0:OUT:0 INSTR_LOG:1|const#5#||0 VAR: const#5 DATATYPE: ANYINT,
    RF:4:IN:0:REG:3 = B:29 STAGE:-1 VAR: const#5 DATATYPE: ANYINT,
    //  IN:ADDER_2: ( const#7 ) = OR( const#3 == UNITRF_1_3[4], const#4 == UNITRF_0_4[1] )
    // OUT:ADDER_2: OR => ( const#7 == UNITRF_0_2[3] )
    //  IN:ADDER_1: ( const#6 ) = OR( const#2 == UNITRF_1_2[2], const#4 == UNITRF_0_3[3] )
    // OUT:ADDER_1: OR => ( const#6 == UNITRF_0_4[4] )
    //  IN:ADDER_0: ( const#5 ) = OR( hw_const#1 == UNITRF_1_1[0], const#4 == UNITRF_0_2[3] )
    // OUT:ADDER_0: OR => ( const#5 == UNITRF_0_3[3] )
    DEAD_REGS: {  };
instr: 15
    MC: OP: NONE LINE:-1,
    U7: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U0: OP: ILT32 LINE:55 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:55
    U2: OP: ILT32 LINE:54 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:54
    U1: OP: ILT32 LINE:53 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:53
    B:38 = RF:18:OUT:1:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:2 = B:38 VAR: hw_const#0 DATATYPE: ANYINT,
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|const#8#||0 VAR: const#8 DATATYPE: ANYINT,
    RF:4:IN:0:REG:3 = B:27 STAGE:-1 VAR: const#8 DATATYPE: ANYINT,
    B:12 = RF:3:OUT:0:REG:3 VAR: const#7 DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: const#7 DATATYPE: ANYINT,
    B:13 = RF:7:OUT:0:REG:3 VAR: bottom_margin DATATYPE: INT,
    U0:IN:1 = B:13 VAR: bottom_margin DATATYPE: INT,
    B:16 = RF:5:OUT:0:REG:4 VAR: const#6 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#6 DATATYPE: ANYINT,
    B:17 = RF:9:OUT:0:REG:2 VAR: bottom_margin DATATYPE: INT,
    U2:IN:1 = B:17 VAR: bottom_margin DATATYPE: INT,