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📄 idxgen_kc.uc

📁 H.264完整的C语言代码和DCT的代码
💻 UC
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// microassembly program:  D:\working\im_apps\h264\idxgen_kc.i
// machine description:    gold8.md
// KERNELDEF: instrs: 62 params: o 0 r 1 r 2 blocks: 3 27 2  35 1  0 -1  SWP_block_depth: 3 -1 0 -1 func_name: idxGen block_io_counts: 3 1 0 0 1 32 0 0 
PARAMS: SCHED_METHOD: COS UC_BITS: 497
         NUM_INPUT_STREAMS: 0 NUM_OUTPUT_STREAMS: 1

// RESULTS: -rs 0, -rf 0
//   block: 0 best: 13 achieved: 27 (lines: 1-65, instrs: 0-26)
//   block: 1 best: 35 achieved: 35 (lines: 66-93, instrs: 27-61)
//   block: 2 best: 0 achieved: 0 (lines: none, instrs: none)

instr: 0
    MC: OP: NONE LINE:-1 UCRF_RD:2,
    U4: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U7: OP: COMMUCDATA LINE:26 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:26
    B:44 = RF:18:OUT:7:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U4:IN:2 = B:44 VAR: hw_const#0 DATATYPE: ANYINT,
    B:21 = RF:13:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U4:IN:1 = B:21 VAR: hw_const#1 DATATYPE: ANYINT,
    B:35 = U4:OUT:1 INSTR_LOG:1|const#1#||1 VAR: const#1 DATATYPE: ANYINT,
    RF:4:IN:0:REG:1 = B:35 STAGE:-1 VAR: const#1 DATATYPE: ANYINT,
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
    B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|parms#||0 VAR: parms DATATYPE: INT,
    RF:11:IN:0:REG:1 = B:27 STAGE:-1 VAR: parms DATATYPE: INT,
    //  IN:MULTIPLIER_1: ( const#1 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#1 == MULRF_1_1[0] )
    // OUT:MULTIPLIER_1: SELECT => ( const#1 == UNITRF_0_3[1] )
    //  IN:COMM_SCHED_0: ( parms ) = COMMUCDATA( hw_const#8 == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_params == UCRF_0[2] )
    // OUT:COMM_SCHED_0: COMMUCDATA => ( parms == MULRF_0_1[1] )
    DEAD_REGS: {  };
instr: 1
    MC: OP: UC_DATA_IN LINE:-1 IMM:0x88883120 UCRF_WR:3 STAGES:-1,
    U1: OP: SHIFT32 LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U7: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    B:14 = RF:4:OUT:0:REG:1 VAR: const#1 DATATYPE: ANYINT,
    U1:IN:0 = B:14 VAR: const#1 DATATYPE: ANYINT,
    B:15 = RF:8:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: hw_const#1 DATATYPE: ANYINT,
    B:30 = U1:OUT:0 INSTR_LOG:1|const#2#||0 VAR: const#2 DATATYPE: ANYINT,
    RF:3:IN:0:REG:4 = B:30 STAGE:-1 VAR: const#2 DATATYPE: ANYINT,
    RF:9:IN:0:REG:3 = B:30 STAGE:-1 VAR: const#2 DATATYPE: ANYINT,
    RF:7:IN:0:REG:1 = B:30 STAGE:-1 VAR: const#2 DATATYPE: ANYINT,
    RF:8:IN:0:REG:2 = B:30 STAGE:-1 VAR: const#2 DATATYPE: ANYINT,
    B:38 = RF:18:OUT:1:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:2 = B:38 VAR: hw_const#0 DATATYPE: ANYINT,
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|const#8#||0 VAR: const#8 DATATYPE: ANYINT,
    RF:5:IN:0:REG:3 = B:27 STAGE:-1 VAR: const#8 DATATYPE: ANYINT,
    RF:4:IN:0:REG:1 = B:27 STAGE:-1 VAR: const#8 DATATYPE: ANYINT,
    //  IN:ADDER_1: ( const#2 ) = SHIFT32( const#1 == UNITRF_0_3[1], hw_const#1 == UNITRF_1_2[0] )
    // OUT:ADDER_1: SHIFT32 => ( const#2 == UNITRF_0_2[4], const#2 == UNITRF_1_3[3], const#2 == UNITRF_1_1[1], const#2 == UNITRF_1_2[2] )
    //  IN:COMM_SCHED_0: ( const#8 ) = SELECT( hw_const#0 == CCRF_0[0], hw_const#8 == PERMRF_0[0] )
    // OUT:COMM_SCHED_0: SELECT => ( const#8 == UNITRF_0_4[3], const#8 == UNITRF_0_3[1] )
    // OUT:MC_0: UC_DATA_IN => ( uc_const#0x88883120 == UCRF_0[3] )
    DEAD_REGS: {  };
instr: 2
    MC: OP: NONE LINE:-1 UCRF_RD:3,
    U1: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U7: OP: COMMUCDATA LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    B:15 = RF:8:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: hw_const#1 DATATYPE: ANYINT,
    B:14 = RF:4:OUT:0:REG:1 VAR: const#8 DATATYPE: ANYINT,
    U1:IN:0 = B:14 VAR: const#8 DATATYPE: ANYINT,
    B:30 = U1:OUT:0 INSTR_LOG:1|const#9#||0 VAR: const#9 DATATYPE: ANYINT,
    RF:5:IN:0:REG:1 = B:30 STAGE:-1 VAR: const#9 DATATYPE: ANYINT,
    RF:9:IN:0:REG:1 = B:30 STAGE:-1 VAR: const#9 DATATYPE: ANYINT,
    RF:4:IN:0:REG:2 = B:30 STAGE:-1 VAR: const#9 DATATYPE: ANYINT,
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
    B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|unpack#||0 VAR: unpack DATATYPE: BYTE4,
    RF:12:IN:0:REG:1 = B:27 STAGE:-1 VAR: unpack DATATYPE: BYTE4,
    RF:13:IN:0:REG:1 = B:27 STAGE:-1 VAR: unpack DATATYPE: BYTE4,
    //  IN:ADDER_1: ( const#9 ) = OR( hw_const#1 == UNITRF_1_2[0], const#8 == UNITRF_0_3[1] )
    // OUT:ADDER_1: OR => ( const#9 == UNITRF_0_4[1], const#9 == UNITRF_1_3[1], const#9 == UNITRF_0_3[2] )
    //  IN:COMM_SCHED_0: ( unpack ) = COMMUCDATA( hw_const#8 == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_const#0x88883120 == UCRF_0[3] )
    // OUT:COMM_SCHED_0: COMMUCDATA => ( unpack == MULRF_1_0[1], unpack == MULRF_1_1[1] )
    DEAD_REGS: {  };
instr: 3
    MC: OP: NONE LINE:-1,
    U5: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U2: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U4: OP: SHUFFLED LINE:27 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:27
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:10 = RF:6:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U5:IN:0 = B:10 VAR: hw_const#1 DATATYPE: ANYINT,
    B:28 = U5:OUT:0 INSTR_LOG:1|const#1#||0 VAR: const#1 DATATYPE: ANYINT,
    RF:3:IN:0:REG:1 = B:28 STAGE:-1 VAR: const#1 DATATYPE: ANYINT,
    B:16 = RF:5:OUT:0:REG:1 VAR: const#9 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#9 DATATYPE: ANYINT,
    B:17 = RF:9:OUT:0:REG:3 VAR: const#2 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#2 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|const#11#||0 VAR: const#11 DATATYPE: ANYINT,
    RF:8:IN:0:REG:1 = B:31 STAGE:-1 VAR: const#11 DATATYPE: ANYINT,
    RF:10:IN:0:REG:1 = B:31 STAGE:-1 VAR: const#11 DATATYPE: ANYINT,
    B:20 = RF:11:OUT:0:REG:1 VAR: parms DATATYPE: INT,
    U4:IN:0 = B:20 VAR: parms DATATYPE: INT,
    B:21 = RF:13:OUT:0:REG:1 VAR: unpack DATATYPE: BYTE4,
    U4:IN:1 = B:21 VAR: unpack DATATYPE: BYTE4,
    B:35 = U4:OUT:1 INSTR_LOG:1|type#|params2_second#||1|0 VAR: type DATATYPE: INT,
    RF:5:IN:0:REG:2 = B:35 STAGE:-1 VAR: type DATATYPE: INT,
    RF:7:IN:0:REG:2 = B:35 STAGE:-1 VAR: type DATATYPE: INT,
    RF:4:IN:0:REG:5 = B:35 STAGE:-1 VAR: type DATATYPE: INT,
    RF:9:IN:0:REG:2 = B:35 STAGE:-1 VAR: type DATATYPE: INT,
    B:34 = U4:OUT:0 INSTR_LOG:1|type#|params2_second#||1|0 VAR: params2_second DATATYPE: INT,
    RF:6:IN:0:REG:1 = B:34 STAGE:-1 VAR: params2_second DATATYPE: INT,
    //  IN:DIVIDER_0: ( const#1 ) = NSELECT( hw_const#0 == CCRF_0[0], hw_const#1 == UNITRF_1_0[0] )
    // OUT:DIVIDER_0: NSELECT => ( const#1 == UNITRF_0_2[1] )
    //  IN:ADDER_2: ( const#11 ) = OR( const#9 == UNITRF_0_4[1], const#2 == UNITRF_1_3[3] )
    // OUT:ADDER_2: OR => ( const#11 == UNITRF_1_2[1], const#11 == MULRF_0_0[1] )
    //  IN:MULTIPLIER_1: ( type, params2_second ) = SHUFFLED( parms == MULRF_0_1[1], unpack == MULRF_1_1[1] )
    // OUT:MULTIPLIER_1: SHUFFLED => ( type == UNITRF_0_4[2], type == UNITRF_1_1[2], type == UNITRF_0_3[5], type == UNITRF_1_3[2], params2_second == UNITRF_1_0[1] )
    DEAD_REGS: {  };
instr: 4
    MC: OP: NONE LINE:-1 UCRF_RD:1,
    U0: OP: SHIFT32 LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U7: OP: COMMUCDATA LINE:22 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:22
    B:12 = RF:3:OUT:0:REG:1 VAR: const#1 DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: const#1 DATATYPE: ANYINT,
    B:13 = RF:7:OUT:0:REG:1 VAR: const#2 DATATYPE: ANYINT,
    U0:IN:1 = B:13 VAR: const#2 DATATYPE: ANYINT,
    B:29 = U0:OUT:0 INSTR_LOG:1|const#4#||0 VAR: const#4 DATATYPE: ANYINT,
    RF:3:IN:0:REG:3 = B:29 STAGE:-1 VAR: const#4 DATATYPE: ANYINT,
    RF:8:IN:0:REG:3 = B:29 STAGE:-1 VAR: const#4 DATATYPE: ANYINT,
    RF:5:IN:0:REG:1 = B:29 STAGE:-1 VAR: const#4 DATATYPE: ANYINT,
    RF:4:IN:0:REG:3 = B:29 STAGE:-1 VAR: const#4 DATATYPE: ANYINT,
    RF:7:IN:0:REG:1 = B:29 STAGE:-1 VAR: const#4 DATATYPE: ANYINT,
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
    B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|size#||0 VAR: size DATATYPE: INT,
    RF:10:IN:0:REG:2 = B:27 STAGE:-1 VAR: size DATATYPE: INT,
    //  IN:ADDER_0: ( const#4 ) = SHIFT32( const#1 == UNITRF_0_2[1], const#2 == UNITRF_1_1[1] )
    // OUT:ADDER_0: SHIFT32 => ( const#4 == UNITRF_0_2[3], const#4 == UNITRF_1_2[3], const#4 == UNITRF_0_4[1], const#4 == UNITRF_0_3[3], const#4 == UNITRF_1_1[1] )
    //  IN:COMM_SCHED_0: ( size ) = COMMUCDATA( hw_const#8 == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_size == UCRF_0[1] )
    // OUT:COMM_SCHED_0: COMMUCDATA => ( size == MULRF_0_0[2] )
    DEAD_REGS: {  };
instr: 5
    MC: OP: NONE LINE:-1,
    U1: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    U3: OP: SHUFFLED LINE:23 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:23
    B:15 = RF:8:OUT:0:REG:1 VAR: const#11 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: const#11 DATATYPE: ANYINT,
    B:14 = RF:4:OUT:0:REG:3 VAR: const#4 DATATYPE: ANYINT,
    U1:IN:0 = B:14 VAR: const#4 DATATYPE: ANYINT,
    B:30 = U1:OUT:0 INSTR_LOG:1|const#15#||0 VAR: const#15 DATATYPE: ANYINT,
    RF:3:IN:0:REG:2 = B:30 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    RF:5:IN:0:REG:4 = B:30 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    RF:4:IN:0:REG:1 = B:30 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    B:18 = RF:10:OUT:0:REG:2 VAR: size DATATYPE: INT,
    U3:IN:0 = B:18 VAR: size DATATYPE: INT,
    B:19 = RF:12:OUT:0:REG:1 VAR: unpack DATATYPE: BYTE4,
    U3:IN:1 = B:19 VAR: unpack DATATYPE: BYTE4,
    B:33 = U3:OUT:1 INSTR_LOG:1|height#|width#||1|0 VAR: height DATATYPE: INT,
    RF:9:IN:0:REG:4 = B:33 STAGE:-1 VAR: height DATATYPE: INT,
    B:32 = U3:OUT:0 INSTR_LOG:1|height#|width#||1|0 VAR: width DATATYPE: INT,
    RF:7:IN:0:REG:5 = B:32 STAGE:-1 VAR: width DATATYPE: INT,
    RF:13:IN:0:REG:2 = B:32 STAGE:-1 VAR: width DATATYPE: INT,
    RF:14:IN:0:REG:1 = B:32 STAGE:-1 VAR: width DATATYPE: INT,
    RF:12:IN:0:REG:1 = B:32 STAGE:-1 VAR: width DATATYPE: INT,
    RF:15:IN:0:REG:1 = B:32 STAGE:-1 VAR: width DATATYPE: INT,
    RF:8:IN:0:REG:7 = B:32 STAGE:-1 VAR: width DATATYPE: INT,
    //  IN:ADDER_1: ( const#15 ) = OR( const#11 == UNITRF_1_2[1], const#4 == UNITRF_0_3[3] )
    // OUT:ADDER_1: OR => ( const#15 == UNITRF_0_2[2], const#15 == UNITRF_0_4[4], const#15 == UNITRF_0_3[1] )
    //  IN:MULTIPLIER_0: ( height, width ) = SHUFFLED( size == MULRF_0_0[2], unpack == MULRF_1_0[1] )
    // OUT:MULTIPLIER_0: SHUFFLED => ( height == UNITRF_1_3[4], width == UNITRF_1_1[5], width == MULRF_1_1[2], width == UNITRF_CID_0[1], width == MULRF_1_0[1], width == PERMRF_0[1], width == UNITRF_1_2[7] )
    DEAD_REGS: {  };
instr: 6
    MC: OP: NONE LINE:-1,
    U2: OP: AND LINE:46 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:46
    U0: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:-1
    B:17 = RF:9:OUT:0:REG:4 VAR: height DATATYPE: INT,
    U2:IN:1 = B:17 VAR: height DATATYPE: INT,
    B:16 = RF:5:OUT:0:REG:4 VAR: const#15 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#15 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|bottom_margin#||0 VAR: bottom_margin DATATYPE: INT,
    RF:7:IN:0:REG:3 = B:31 STAGE:-1 VAR: bottom_margin DATATYPE: INT,
    RF:2:IN:0:REG:1 = B:31 STAGE:-1 VAR: bottom_margin DATATYPE: INT,
    B:13 = RF:7:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U0:IN:1 = B:13 VAR: hw_const#1 DATATYPE: ANYINT,
    B:12 = RF:3:OUT:0:REG:4 VAR: const#2 DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: const#2 DATATYPE: ANYINT,
    B:29 = U0:OUT:0 INSTR_LOG:1|const#3#||0 VAR: const#3 DATATYPE: ANYINT,
    RF:9:IN:0:REG:4 = B:29 STAGE:-1 VAR: const#3 DATATYPE: ANYINT,
    RF:3:IN:0:REG:1 = B:29 STAGE:-1 VAR: const#3 DATATYPE: ANYINT,
    RF:5:IN:0:REG:4 = B:29 STAGE:-1 VAR: const#3 DATATYPE: ANYINT,
    RF:4:IN:0:REG:4 = B:29 STAGE:-1 VAR: const#3 DATATYPE: ANYINT,
    //  IN:ADDER_2: ( bottom_margin ) = AND( height == UNITRF_1_3[4], const#15 == UNITRF_0_4[4] )
    // OUT:ADDER_2: AND => ( bottom_margin == UNITRF_1_1[3], bottom_margin == UNITRF_0_1[1] )
    //  IN:ADDER_0: ( const#3 ) = OR( hw_const#1 == UNITRF_1_1[0], const#2 == UNITRF_0_2[4] )
    // OUT:ADDER_0: OR => ( const#3 == UNITRF_1_3[4], const#3 == UNITRF_0_2[1], const#3 == UNITRF_0_4[4], const#3 == UNITRF_0_3[4] )
    DEAD_REGS: {  };
instr: 7
    MC: OP: NONE LINE:-1,
    U0: OP: ILT32 LINE:47 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:47
    U1: OP: IEQ32 LINE:45 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:45
    U2: OP: IEQ32 LINE:45 STAGE:-1, // D:\working\im_apps\h264\idxgen_kc.i:45
    B:13 = RF:7:OUT:0:REG:3 VAR: bottom_margin DATATYPE: INT,
    U0:IN:1 = B:13 VAR: bottom_margin DATATYPE: INT,
    B:12 = RF:3:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,

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