me_fast_jitter1_kc.uc

H.264完整的C语言代码和DCT的代码

    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:10 = RF:6:OUT:0:REG:3 VAR: margin DATATYPE: INT,
    U5:IN:0 = B:10 VAR: margin DATATYPE: INT,
    B:28 = U5:OUT:0 INSTR_LOG:1|margin#||0 VAR: margin DATATYPE: INT,
    RF:3:IN:0:REG:4 = B:28 STAGE:-1 VAR: margin DATATYPE: INT,
    B:16 = RF:5:OUT:0:REG:4 VAR: const#-9 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#-9 DATATYPE: ANYINT,
    B:17 = RF:9:OUT:0:REG:3 VAR: const#-8 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#-8 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|const#-16#||0 VAR: const#-16 DATATYPE: ANYINT,
    RF:7:IN:0:REG:7 = B:31 STAGE:-1 VAR: const#-16 DATATYPE: ANYINT,
    RF:4:IN:0:REG:3 = B:31 STAGE:-1 VAR: const#-16 DATATYPE: ANYINT,
    RF:9:IN:0:REG:3 = B:31 STAGE:-1 VAR: const#-16 DATATYPE: ANYINT,
    RF:12:IN:0:REG:3 = B:31 STAGE:-1 VAR: const#-16 DATATYPE: ANYINT,
    //  IN:ADDER_1: ( tmp#136 ) = IADD32( tmp#135 == UNITRF_1_2[6], right_margin == UNITRF_0_3[3] )
    //  IN:DIVIDER_0: ( margin ) = NSELECT( hw_const#0 == CCRF_0[0], margin == UNITRF_1_0[3] )
    // OUT:DIVIDER_0: NSELECT => ( margin == UNITRF_0_2[4] )
    //  IN:ADDER_2: ( const#-16 ) = AND( const#-9 == UNITRF_0_4[4], const#-8 == UNITRF_1_3[3] )
    // OUT:ADDER_2: AND => ( const#-16 == UNITRF_1_1[7], const#-16 == UNITRF_0_3[3], const#-16 == UNITRF_1_3[3], const#-16 == MULRF_1_0[3] )
    DEAD_REGS: {  };
instr: 17
    MC: OP: NONE LINE:-1,
    U0: OP: SHIFT32 LINE:53 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:53
    U2: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:-1
    B:30 = U1:OUT:0 INSTR_LOG:2|tmp#136#||0 VAR: tmp#136 DATATYPE: INT,
    RF:5:IN:0:REG:1 = B:30 STAGE:-1 VAR: tmp#136 DATATYPE: INT,
    B:12 = RF:3:OUT:0:REG:4 VAR: margin DATATYPE: INT,
    U0:IN:0 = B:12 VAR: margin DATATYPE: INT,
    B:13 = RF:7:OUT:0:REG:7 VAR: const#-16 DATATYPE: ANYINT,
    U0:IN:1 = B:13 VAR: const#-16 DATATYPE: ANYINT,
    B:29 = U0:OUT:0 INSTR_LOG:1|tmp#123#||0 VAR: tmp#123 DATATYPE: INT,
    RF:7:IN:0:REG:3 = B:29 STAGE:-1 VAR: tmp#123 DATATYPE: INT,
    B:17 = RF:9:OUT:0:REG:0 VAR: hw_const#1 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: hw_const#1 DATATYPE: ANYINT,
    B:16 = RF:5:OUT:0:REG:1 VAR: const#8 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#8 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|const#9#||0 VAR: const#9 DATATYPE: ANYINT,
    RF:4:IN:0:REG:4 = B:31 STAGE:-1 VAR: const#9 DATATYPE: ANYINT,
    // OUT:ADDER_1: IADD32 => ( tmp#136 == UNITRF_0_4[1] )
    //  IN:ADDER_0: ( tmp#123 ) = SHIFT32( margin == UNITRF_0_2[4], const#-16 == UNITRF_1_1[7] )
    // OUT:ADDER_0: SHIFT32 => ( tmp#123 == UNITRF_1_1[3] )
    //  IN:ADDER_2: ( const#9 ) = OR( hw_const#1 == UNITRF_1_3[0], const#8 == UNITRF_0_4[1] )
    // OUT:ADDER_2: OR => ( const#9 == UNITRF_0_3[4] )
    DEAD_REGS: {  };
instr: 18
    MC: OP: NONE LINE:-1,
    U2: OP: ISUB32 LINE:87 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:87
    U1: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:-1
    U0: OP: AND LINE:53 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:53
    B:16 = RF:5:OUT:0:REG:1 VAR: tmp#136 DATATYPE: INT,
    U2:IN:0 = B:16 VAR: tmp#136 DATATYPE: INT,
    B:17 = RF:9:OUT:0:REG:2 VAR: const#16 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#16 DATATYPE: ANYINT,
    B:14 = RF:4:OUT:0:REG:4 VAR: const#9 DATATYPE: ANYINT,
    U1:IN:0 = B:14 VAR: const#9 DATATYPE: ANYINT,
    B:15 = RF:8:OUT:0:REG:2 VAR: const#2 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: const#2 DATATYPE: ANYINT,
    B:30 = U1:OUT:0 INSTR_LOG:1|const#11#||0 VAR: const#11 DATATYPE: ANYINT,
    RF:7:IN:0:REG:3 = B:30 STAGE:-1 VAR: const#11 DATATYPE: ANYINT,
    B:13 = RF:7:OUT:0:REG:3 VAR: tmp#123 DATATYPE: INT,
    U0:IN:1 = B:13 VAR: tmp#123 DATATYPE: INT,
    B:12 = RF:3:OUT:0:REG:3 VAR: const#255 DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: const#255 DATATYPE: ANYINT,
    B:29 = U0:OUT:0 INSTR_LOG:1|left_margin#||0 VAR: left_margin DATATYPE: INT,
    RF:9:IN:0:REG:6 = B:29 STAGE:-1 VAR: left_margin DATATYPE: INT,
    //  IN:ADDER_2: ( num_cols_to_right ) = ISUB32( tmp#136 == UNITRF_0_4[1], const#16 == UNITRF_1_3[2] )
    //  IN:ADDER_1: ( const#11 ) = OR( const#9 == UNITRF_0_3[4], const#2 == UNITRF_1_2[2] )
    // OUT:ADDER_1: OR => ( const#11 == UNITRF_1_1[3] )
    //  IN:ADDER_0: ( left_margin ) = AND( tmp#123 == UNITRF_1_1[3], const#255 == UNITRF_0_2[3] )
    // OUT:ADDER_0: AND => ( left_margin == UNITRF_1_3[6] )
    DEAD_REGS: {  };
instr: 19
    MC: OP: NONE LINE:-1,
    U0: OP: OR LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:-1
    U2: OP: ISUB32 LINE:98 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:98
    B:31 = U2:OUT:0 INSTR_LOG:2|num_cols_to_right#||0 VAR: num_cols_to_right DATATYPE: INT,
    RF:4:IN:0:REG:4 = B:31 STAGE:-1 VAR: num_cols_to_right DATATYPE: INT,
    RF:11:IN:0:REG:3 = B:31 STAGE:-1 VAR: num_cols_to_right DATATYPE: INT,
    B:13 = RF:7:OUT:0:REG:3 VAR: const#11 DATATYPE: ANYINT,
    U0:IN:1 = B:13 VAR: const#11 DATATYPE: ANYINT,
    B:12 = RF:3:OUT:0:REG:2 VAR: const#4 DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: const#4 DATATYPE: ANYINT,
    B:29 = U0:OUT:0 INSTR_LOG:1|const#15#||0 VAR: const#15 DATATYPE: ANYINT,
    RF:9:IN:0:REG:4 = B:29 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    RF:12:IN:0:REG:5 = B:29 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    RF:8:IN:0:REG:6 = B:29 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    RF:13:IN:0:REG:6 = B:29 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    RF:7:IN:0:REG:3 = B:29 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    RF:6:IN:0:REG:3 = B:29 STAGE:-1 VAR: const#15 DATATYPE: ANYINT,
    B:16 = RF:5:OUT:0:REG:3 VAR: const#16 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: const#16 DATATYPE: ANYINT,
    B:17 = RF:9:OUT:0:REG:6 VAR: left_margin DATATYPE: INT,
    U2:IN:1 = B:17 VAR: left_margin DATATYPE: INT,
    // OUT:ADDER_2: ISUB32 => ( num_cols_to_right == UNITRF_0_3[4], num_cols_to_right == MULRF_0_1[3] )
    //  IN:ADDER_0: ( const#15 ) = OR( const#11 == UNITRF_1_1[3], const#4 == UNITRF_0_2[2] )
    // OUT:ADDER_0: OR => ( const#15 == UNITRF_1_3[4], const#15 == MULRF_1_0[5], const#15 == UNITRF_1_2[6], const#15 == MULRF_1_1[6], const#15 == UNITRF_1_1[3], const#15 == UNITRF_1_0[3] )
    //  IN:ADDER_2: ( tmp#142 ) = ISUB32( const#16 == UNITRF_0_4[3], left_margin == UNITRF_1_3[6] )
    DEAD_REGS: {  };
instr: 20
    MC: OP: NONE LINE:-1,
    U1: OP: ILT32 LINE:88 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:88
    U5: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:-1
    B:14 = RF:4:OUT:0:REG:4 VAR: num_cols_to_right DATATYPE: INT,
    U1:IN:0 = B:14 VAR: num_cols_to_right DATATYPE: INT,
    B:15 = RF:8:OUT:0:REG:6 VAR: const#15 DATATYPE: ANYINT,
    U1:IN:1 = B:15 VAR: const#15 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:2|tmp#142#||0 VAR: tmp#142 DATATYPE: INT,
    RF:5:IN:0:REG:1 = B:31 STAGE:-1 VAR: tmp#142 DATATYPE: INT,
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:10 = RF:6:OUT:0:REG:5 VAR: const#-2 DATATYPE: ANYINT,
    U5:IN:0 = B:10 VAR: const#-2 DATATYPE: ANYINT,
    B:28 = U5:OUT:0 INSTR_LOG:1|const#-2#||0 VAR: const#-2 DATATYPE: ANYINT,
    RF:9:IN:0:REG:8 = B:28 STAGE:-1 VAR: const#-2 DATATYPE: ANYINT,
    //  IN:ADDER_1: ( tmp#138 ) = ILT32( num_cols_to_right == UNITRF_0_3[4], const#15 == UNITRF_1_2[6] )
    // OUT:ADDER_2: ISUB32 => ( tmp#142 == UNITRF_0_4[1] )
    //  IN:DIVIDER_0: ( const#-2 ) = NSELECT( hw_const#0 == CCRF_0[0], const#-2 == UNITRF_1_0[5] )
    // OUT:DIVIDER_0: NSELECT => ( const#-2 == UNITRF_1_3[8] )
    DEAD_REGS: {  };
instr: 21
    MC: OP: NONE LINE:-1,
    U2: OP: SHIFT32 LINE:98 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:98
    B:46 = U1:OUT:0 INSTR_LOG:2|tmp#138#||0 VAR: tmp#138 DATATYPE: CC,
    RF:18:IN:0:REG:1 = B:46 STAGE:-1 VAR: tmp#138 DATATYPE: CC,
    B:16 = RF:5:OUT:0:REG:1 VAR: tmp#142 DATATYPE: INT,
    U2:IN:0 = B:16 VAR: tmp#142 DATATYPE: INT,
    B:17 = RF:9:OUT:0:REG:8 VAR: const#-2 DATATYPE: ANYINT,
    U2:IN:1 = B:17 VAR: const#-2 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|idx#||0 VAR: idx DATATYPE: INT,
    RF:4:IN:0:REG:11 = B:31 STAGE:-1 VAR: idx DATATYPE: INT,
    RF:12:IN:0:REG:4 = B:31 STAGE:-1 VAR: idx DATATYPE: INT,
    RF:15:IN:0:REG:3 = B:31 STAGE:-1 VAR: idx DATATYPE: INT,
    RF:14:IN:0:REG:3 = B:31 STAGE:-1 VAR: idx DATATYPE: INT,
    RF:10:IN:0:REG:1 = B:31 STAGE:-1 VAR: idx DATATYPE: INT,
    RF:13:IN:0:REG:5 = B:31 STAGE:-1 VAR: idx DATATYPE: INT,
    // OUT:ADDER_1: ILT32 => ( tmp#138 == CCRF_0[1] )
    //  IN:ADDER_2: ( idx ) = SHIFT32( tmp#142 == UNITRF_0_4[1], const#-2 == UNITRF_1_3[8] )
    // OUT:ADDER_2: SHIFT32 => ( idx == UNITRF_0_3[11], idx == MULRF_1_0[4], idx == PERMRF_0[3], idx == UNITRF_CID_0[3], idx == MULRF_0_0[1], idx == MULRF_1_1[5] )
    DEAD_REGS: {  };
instr: 22
    MC: OP: NONE LINE:-1,
    U4: OP: SELECT LINE:88 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:88
    U3: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:-1
    B:44 = RF:18:OUT:7:REG:1 VAR: tmp#138 DATATYPE: CC,
    U4:IN:2 = B:44 VAR: tmp#138 DATATYPE: CC,
    B:20 = RF:11:OUT:0:REG:3 VAR: num_cols_to_right DATATYPE: INT,
    U4:IN:0 = B:20 VAR: num_cols_to_right DATATYPE: INT,
    B:21 = RF:13:OUT:0:REG:6 VAR: const#15 DATATYPE: ANYINT,
    U4:IN:1 = B:21 VAR: const#15 DATATYPE: ANYINT,
    B:35 = U4:OUT:1 INSTR_LOG:1|tmp#139#||1 VAR: tmp#139 DATATYPE: INT,
    RF:12:IN:0:REG:6 = B:35 STAGE:-1 VAR: tmp#139 DATATYPE: INT,
    B:43 = RF:18:OUT:6:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U3:IN:2 = B:43 VAR: hw_const#0 DATATYPE: ANYINT,
    B:18 = RF:10:OUT:0:REG:1 VAR: idx DATATYPE: INT,
    U3:IN:0 = B:18 VAR: idx DATATYPE: INT,
    B:33 = U3:OUT:1 INSTR_LOG:1|idx#||1 VAR: idx DATATYPE: INT,
    RF:17:IN:0:REG:1 = B:33 STAGE:-1 VAR: idx DATATYPE: INT,
    //  IN:MULTIPLIER_1: ( tmp#139 ) = SELECT( tmp#138 == CCRF_0[1], num_cols_to_right == MULRF_0_1[3], const#15 == MULRF_1_1[6] )
    // OUT:MULTIPLIER_1: SELECT => ( tmp#139 == MULRF_1_0[6] )
    //  IN:MULTIPLIER_0: ( idx ) = NSELECT( hw_const#0 == CCRF_0[0], idx == MULRF_0_0[1] )
    // OUT:MULTIPLIER_0: NSELECT => ( idx == SPIDXRF_1[1] )
    DEAD_REGS: {  };
instr: 23
    MC: OP: NONE LINE:-1,
    U3: OP: SELECT LINE:88 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:88
    U4: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:-1
    U5: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:-1
    B:43 = RF:18:OUT:6:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U3:IN:2 = B:43 VAR: hw_const#0 DATATYPE: ANYINT,
    B:19 = RF:12:OUT:0:REG:6 VAR: tmp#139 DATATYPE: INT,
    U3:IN:1 = B:19 VAR: tmp#139 DATATYPE: INT,
    B:33 = U3:OUT:1 INSTR_LOG:1|right_range#174#||1 VAR: right_range#174 DATATYPE: INT,
    RF:5:IN:0:REG:1 = B:33 STAGE:-1 VAR: right_range#174 DATATYPE: INT,
    RF:4:IN:0:REG:8 = B:33 STAGE:-1 VAR: right_range#174 DATATYPE: INT,
    B:44 = RF:18:OUT:7:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U4:IN:2 = B:44 VAR: hw_const#0 DATATYPE: ANYINT,
    B:21 = RF:13:OUT:0:REG:5 VAR: idx DATATYPE: INT,
    U4:IN:1 = B:21 VAR: idx DATATYPE: INT,
    B:35 = U4:OUT:1 INSTR_LOG:1|idx#||1 VAR: idx DATATYPE: INT,
    RF:17:IN:0:REG:1 = B:35 STAGE:-1 VAR: idx DATATYPE: INT,
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:10 = RF:6:OUT:0:REG:4 VAR: const#-8 DATATYPE: ANYINT,
    U5:IN:0 = B:10 VAR: const#-8 DATATYPE: ANYINT,
    B:28 = U5:OUT:0 INSTR_LOG:1|const#-8#||0 VAR: const#-8 DATATYPE: ANYINT,
    RF:8:IN:0:REG:6 = B:28 STAGE:-1 VAR: const#-8 DATATYPE: ANYINT,
    //  IN:MULTIPLIER_0: ( right_range#174 ) = SELECT( hw_const#0 == CCRF_0[0], tmp#139 == MULRF_1_0[6] )
    // OUT:MULTIPLIER_0: SELECT => ( right_range#174 == UNITRF_0_4[1], right_range#174 == UNITRF_0_3[8] )
    //  IN:MULTIPLIER_1: ( idx ) = SELECT( hw_const#0 == CCRF_0[0], idx == MULRF_1_1[5] )
    // OUT:MULTIPLIER_1: SELECT => ( idx == SPIDXRF_1[1] )
    //  IN:DIVIDER_0: ( const#-8 ) = NSELECT( hw_const#0 == CCRF_0[0], const#-8 == UNITRF_1_0[4] )
    // OUT:DIVIDER_0: NSELECT => ( const#-8 == UNITRF_1_2[6] )
    DEAD_REGS: {  };
instr: 24
    MC: OP: NONE LINE:-1,
    U2: OP: IADD32 LINE:95 STAGE:-1, // D:\working\im_apps\h264\me_fast_jitter1_kc.i:95